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CCD Signal Processor with Precision TimingTM Generator AD9929
FEATURES
36 MSPS correlated double sampler (CDS) 12-bit 36 MHz A/D converter On-chip vertical driver for CCD image sensor On-chip horizontal driver for CCD image sensor 6 dB to 40 dB variable gain amplifier (VGA) Black level clamp with variable level control Complete on-chip timing generator Precision Timing core with 0.58 ns resolution 2-phase H-clock modes 4-phase vertical transfer clocks Electronic and mechanical shutter modes On-chip sync generator with external sync option 64-lead, plastic ball, 9 x 9 grid array Pb-free package
PRODUCT DESCRIPTION
The AD9929 is a highly integrated CCD signal processor for digital still camera and digital video camera applications. It includes a complete analog front end with A/D conversion, combined with a full-function, programmable timing generator. The AD9929 also includes horizontal and vertical clock drivers, which allow direct connection to the CCD image sensor. The AD9929 is specified at pixel rates of up to 36 MHz. The analog front end includes black level clamping, a CDS, a VGA, and a 12-bit A/D converter. The timing generator provides all the necessary CCD clocks: RG-clock, H-clocks, V-clocks, sensor gate pulses, a substrate clock, and a substrate bias pulse. Operation is programmed using a 3-wire serial interface. The AD9929 is packaged in a 64-lead CSPBGA. It is specified over an operating temperature range of -25C to +85C.
APPLICATION
Digital still cameras Digital video camcorders
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
AD9929
CCDIN CDS
6dB TO 40dB VREF VGA ADC 12 DOUT
CLAMP INTERNAL CLOCKS VSUB RG 2 H1, H2 V1, V2, V3, V4 SUBCK 4 VERTICAL DRIVERS SYNC GENERATOR INTERNAL REGISTERS HORIZONTAL DRIVERS PRECISION TIMING GENERATOR DCLK1 FD/DCLK2 MSHUT STROBE
HD
VD
SYNC
CLI
SL SCKS
DI
Figure 1.
Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
04593-0-001
AD9929 TABLE OF CONTENTS
Specifications..................................................................................... 3 Digital Specifications ................................................................... 4 Analog Specifications................................................................... 4 Timing Specifications .................................................................. 5 Vertical Driver Specifications ..................................................... 5 Terminology ...................................................................................... 7 Absolute Maximum Ratings............................................................ 8 Pin Configuration and Functional Descriptions.......................... 9 Equivalent Input Circuits .............................................................. 10 System Overview ............................................................................ 18 Theory of Operation ...................................................................... 19 Modes of Operation ................................................................... 19 Horizontal and Vertical Counters ............................................ 19 CLI Input Clock Divider............................................................ 19 Gray Code Registers................................................................... 19 Serial Interface Timing .............................................................. 20 Analog Front End Description and Operation....................... 22 Precision Timing, High Speed Timing Generation ............... 23 H Driver and RG Outputs ......................................................... 23 Digital Data Outputs.................................................................. 26 External Synchronization (Master Mode)................................... 27 Horizontal and Vertical Synchronous Timing............................ 28 Special Note about the HDLEN Register ................................ 28 Horizontal Clamping and Blanking ............................................. 29 Controlling CLPOB Clamp Pulse Timing .............................. 29 Controlling CLPOB Clamp Pulse Outputs ............................. 30 H1 and H2 Blanking .................................................................. 31 VGATE Masking of XV1 to XV4 and CLPOB Outputs............ 33 Vertical Timing Generation .......................................................... 34 Creating Vertical Sequences...................................................... 34 Special Vertical Sweep Mode Operation ................................. 39 Special Vertical Timing (SPATS).............................................. 40 V1 to V4 and SUBCK Output Polarities ..................................... 43 Timing Control............................................................................... 46 Electronic Shutter Timing Control .......................................... 46 VSG Timing ................................................................................ 48 VSUB Timing.............................................................................. 49 MSHUT Timing ......................................................................... 50 Strobe Timing ............................................................................. 52 Digital I/O States for Different Operating Conditions.............. 53 Power Supply Sequencing ............................................................. 54 Recommended Power-Up Supply Sequencing....................... 54 Recommended Power-Down Supply Sequencing ................. 54 Initial Start-Up Sequence .......................................................... 55 Standby Mode Operation .......................................................... 56 Shut-Down Mode Operation.................................................... 57 Applications Where the CLI Clock Frequency Changes During Operation....................................................................... 58 Circuit Layout Information........................................................... 60 Outline Dimensions ....................................................................... 62 Ordering Guide .......................................................................... 62
REVISION HISTORY
Revision A 2/04--Data Sheet Changed from Rev. 0 to Rev. A Replaced Figure....................................................................................21 1/04--Revision 0: Initial Version
Rev. A | Page 2 of 64
AD9929 SPECIFICATIONS
Table 1.
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE AVDD (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RGVDD (RG Driver) HVDD (H1 to H2 Drivers) DRVDD (Data Output Drivers) DVDD (Digital) VERTICAL DRIVER SUPPLY VOLTAGE VDD (Vertical Driver Input Logic Supply) VH1, VH2 (Vertical Driver High Supply) VM1, VM2 (Vertical Driver Mid Supply) VL (Vertical Driver Low Supply for 3 Level and 2 Level) AFETG POWER DISSIPATION 36 MHz, Typ Supply Levels, 100 pF H1 to H2 Loading Power from HVDD Only1 Power-down Mode (AFE and Digital in Standby Operation) VERTICAL DRIVER POWER DISSIPATION2 (6000 pF V1 to V4 Loading, 1000 pF SUBCK Loading) Power from VDD Power from VH1 Power from VH2 Power from VL MAXIMUM CLOCK RATE (CLI) AD9929 Min -25 -65 2.7 2.7 2.7 2.7 2.7 2.7 2.7 11.5 -1.0 -9.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 15.0 0.0 -7.5 180 36 1 <1.0 23.0 15.0 42.0 36 Typ Max +85 +150 3.6 3.6 3.6 3.6 3.6 3.6 3.6 16.0 1.0 -5.0 Unit C C V V V V V V V V V V mW mW mW mW mW mW mW MHz
1
The total power dissipated by the HVDD supply may be approximated by using the equation: Total HVDD Power = [CLOAD x HVDD x Pixel Frequency] x HVDD x Number of H-Outputs Used. Actual HVDD power may be slightly different than the calculated value because of the stray capacitance inherent in the PCB layout/routing. 2 Vertical driver loads used when characterizing power consumption. Note: actual power depends on the V1 to V4 timing and number of SUBCKs.
V1, V2, V3, V4 SUBCK
6000 pF
1000 pF
INPUT SIGNAL CHARACTERISTICS DEFINED AS FOLLOWS: 500mV TYP RESET TRANSIENT
100mV MAX OPTICAL BLACK PIXEL
1V MAX INPUT SIGNAL RANGE
04593-0-002
Rev. A | Page 3 of 64
AD9929
DIGITAL SPECIFICATIONS
Table 2. RGVDD = HVDD = 2.7 V to 3.6 V, DVDD = DRVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS (Except H and RG) High Level Output Voltage @ IOH = 2 mA Low Level Output Voltage @ IOL = 2 mA RG and H-DRIVER OUTPUTS (H1 to H2) High Level Output Voltage @ Max Current Low Level Output Voltage @ Max Current RG Maximum Output Current (Programmable) H1 and H2 Maximum Output Current (Programmable) Maximum Load Capacitance Symbol VIH VIL IIH IIL CIN VOH VOL VOH VOL Min 2.1 0.6 10 10 10 2.2 0.5 VDD - 0.5 0.5 15 30 100 Typ Max Unit V V A A pF V V V V mA mA pF
ANALOG SPECIFICATIONS
Table 3. AVDD = 3.0 V, fCLI = 36 MHz, TMIN to TMAX, unless otherwise noted.
Parameter CDS Allowable CCD Reset Transient Max Input Range before Saturation Max CCD Black Pixel Amplitude VARIABLE GAIN AMPLIFIER (VGA) Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Low Gain Max Gain BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Min Clamp Level Max Clamp Level A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Accuracy Low Gain (VGA Code = 22) Max Gain (VGA Code = 994) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR) Min Typ 500 1.0 100 2.0 1024 Guaranteed 6 40 255 0 255 10 0.5 Guaranteed 2.0 2.0 1.0 Max Unit mV V p-p mV V p-p Steps Notes See input signal characteristics in Table 1.
dB dB Steps LSB LSB LSB Bits LSB V V V Includes entire signal chain.
LSB measured at ADC output.
6 40 0.1 0.3 40
Rev. A | Page 4 of 64
dB dB % LSB rms dB
Gain = (0.035 x Code) + 5.2 dB. 12 dB gain applied. AC grounded input, 6 dB gain applied. Measured with step change on supply.
AD9929
TIMING SPECIFICATIONS
Table 4. CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 36 MHz, unless otherwise noted.
Parameter MASTER CLOCK, CLI CLI Clock Period CLI High/Low Pulse Width Delay from CLI Rising Edge to Internal Pixel Position 0 AFE CLAMP PULSES1 CLPOB Pulse Width AFE SAMPLE LOCATION1 (See Figure 17) SHP Sample Edge to SHD Sample Edge DATA OUTPUTS Output Delay from DCLK1 Rising Edge (See Figure 19) Pipeline Delay from SHP/SHD Sampling (See Figure 70) SERIAL INTERFACE (See Figure 10 and Figure 11) Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read Symbol tCONV tCLIDLY 4 TS1 tOD tDV fSCLK tLS tLH tDS tDH tOD 20 Min 27.8 13.9 6 10 25 9 9 10 10 10 10 10 10 Typ Max Unit ns ns ns Pixels Pixels ns Cycles MHz ns ns ns ns ns
1
Parameter is programmable.
VERTICAL DRIVER SPECIFICATIONS
Table 5. V1 to V4 load = no load, SUBCK load = no load, VDD = 3.0 V, VL = -7.5 V, VH1 = VH2 = +15.0 V, VM1 = VM2 = GND, fCLI = 36 MHz, unless otherwise noted. Parameter Symbol Min Typ Max Unit LOGIC INPUTS High Level Input Voltage VIH 0.8 (VDD) VDD V Low Level Input Voltage VIL 0 0.3 (VDD) V Propagation Delays, Rise/Fall Times and Output Currents V1 and V3 Outputs (See Figure 43) Delay Times VL to VM1 tPLM1 100 ns VM1 to VH1 tPMH 100 ns VH1 to VM1 tPHM 50 ns VM1 to VL tPML1 50 ns Rise Times VL to VM1 tR1 500 ns VM1 to VH1 tR2 500 ns Fall Times VH1 to VM1 tF1 500 ns VM1 to VL tF2 500 ns Output Currents V1 or V3 @ VL = -7.25 V 10.0 mA V1 or V3 @ VM1 = -0.25 V -5.0 mA V1 or V3 @ VM1 = +0.25 V 5.0 mA V1 or V3 @ VH1 = +14.75 V -7.2 mA
Rev. A | Page 5 of 64
AD9929
Parameter V2 and V4 Outputs (See Figure 43) Delay Times VL to VM2 VM2 to VL Rise Times VL to VM2 Fall Times VM2 to VL Output Currents V2 or V2 @ VL =-7.25 V V2 or V4 @ VM2 = -0.25 V SUBCK Output (See Figure 44) Delay Times VL to VH2 VH2 to VL Rise Times VL to VH2 Fall Times VH2 to VL Output Currents SUBCK @ VL = -7.25 V SUBCK @ VH2 = 14.75 V Symbol Min Typ Max Unit
tPLM2 tPML2 tR3 tF3
100 50 500 500 10.0 -5.0
ns ns ns ns mA mA
tPLH tPHL tR4 tF4
100 50 90 90 5.4 -4.0
ns ns ns ns mA mA
Rev. A | Page 6 of 64
AD9929 TERMINOLOGY
Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. "No missing codes guaranteed to 12-bit resolution" indicates that all 4096 codes, respectively, must be present over all operating conditions. Peak Nonlinearity Peak nonlinearity, a full signal-chain specification, refers to the peak deviation of the output of the AD9929 from a true straight line. The point used as zero scale occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a level 1 and 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC's full-scale range. Total Output Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSBs, and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC full scale/2N codes) when N is the bit resolution of the ADC. For the AD9929, 1 LSB is 0.5 mV. Power Supply Rejection (PSR) The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage.
Rev. A | Page 7 of 64
AD9929 ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter VDD VL VH1, VH2 VM1, VM2 AVDD TCVDD HVDD RGVDD DVDD DRVDD RG Output H1 to H2 Output Digital Outputs Digital Inputs SCK, SL, SDATA REFT, REFB CCDIN With Respect To VDVSS VDVSS VDVSS VDVSS AVSS TCVSS HVSS RGVSS DVSS DRVSS RGVSS HVSS DVSS DVSS DVSS AVSS AVSS Min VDVSS - 0.3 VDVSS - 10.0 VL -0.3 VL - 0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max VDVSS + 4.0 VDVSS + 0.3 VL + 27.0 VL + 27.0 +3.9 +3.9 +3.9 +3.9 +3.9 +3.9 RGVDD + 0.3 HVDD + 0.3 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 Unit V V V V V V V V V V V V V V V V V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Package Thermal Resistance
JA = 61.0 C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulates on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 8 of 64
AD9929 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
A 1 CORNER INDEX AREA 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K
AD9929
TOP VIEW (Not to Scale)
04593-0-003
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin D1 D2 B8 A8 A7 B7 A6 B6 B5 A4 B3 A3 B2 A2 A1 B4 A5 G9 D10 E9 G10 H9 H10 C10 F10 F9 E10 Mnemonic VD HD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 DCLK1 DRVSS DRVDD SUBCK V1 V2 V3 V4 VH1 VM1 VM2 VL VH2 Type1 DIO DIO DO DO DO DO DO DO DO DO DO DO DO DO DO P P DO DO DO DO DO P P P P P Description Vertical Sync Pulse (Input for Slave Mode, Output for Master Mode) Horizontal Sync Pulse (Input for Slave Mode, Output for Master Mode) Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Clock Output Data Output Driver Ground Data Output Driver Supply CCD Substrate Clock (2 Level: VH2, VL) CCD Vertical Transfer Clock (3 Level: VH1, VM1, VL) CCD Vertical Transfer Clock (2 Level: VM2, VL) CCD Vertical Transfer Clock (3 Level: VH1, VM1, VL) CCD Vertical Transfer Clock (2 Level: VM2, VL) Vertical Driver High Supply (High Supply for V1 and V3) Vertical Driver Midsupply (Midsupply for V1 and V3) Vertical Driver Midsupply (Midsupply for V2 and V4) Vertical Driver Low Supply Vertical Driver High Supply for SUBCK Pin B10 J9 A9 G1 F1 E1 E2 F2 G2 H1 J1 H2 C9 C1 K3 J3 J4 J5 J6 J7 J8 K4 K6 J2 K2 K1 K5 K7 K8 K9 K10 J10 D9 B1 C2 A10 B9 Mnemonic VDD VDVSS VSUB H1 H2 HVDD HVSS HVSS HVSS RG RGVDD RGVSS SYNC or VGATE FD or DCLK2 AVDD AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS CLI TCVDD TCVSS CCDIN REFT REFB SDATA SL SCK OUTCONT MSHUT STROBE DVDD DVSS Type1 P P DO DO DO P P P P DO P P DI DI DO DO P P P P P P P P P DI P P AI AO AO DI DI DI DI DO DO P P Description Vertical Driver Input Logic Supply Vertical Driver Ground CCD Substrate Bias CCD Horizontal Clock CCD Horizontal Clock H1 and H2 Driver Supply H1 and H2 Driver Ground H1 and H2 Driver Ground H1 and H2 Driver Ground CCD Reset Gate Clock RG Driver Supply RG Driver Ground External System Sync Input VGATE Input Field Designator Output DCLK2 Output Analog Supply for AFE Analog Ground for AFE Analog Ground for AFE Analog Ground for AFE Analog Ground for AFE Analog Ground for AFE Analog Ground for AFE Analog Ground for AFE Analog Ground for AFE Reference Clock Input Analog Supply for Timing Core Analog Ground for Timing Core CCD Input Signal Voltage Reference Top Bypass Voltage Reference Bottom Bypass 3-Wire Serial Data Input 3-Wire Serial Load Pulse 3-Wire Serial Clock Output Control Mechanical Shutter Pulse Strobe Pulse Digital Supply Digital Ground
1
AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input/Output, P = Power.
Rev. A | Page 9 of 64
AD9929 EQUIVALENT INPUT CIRCUITS
DVDD
AVDD
R
330
AVSS
AVSS
04593-0-004
DVSS
Figure 3. Circuit 1. CCDIN
Figure 5. Circuit 3. Digital Inputs
DVDD
DRVDD
HVDD OR RGVDD
DATA
RG, H1 H2
THREESTATE
DOUT
04593-0-006
OUTPUT ENABLE
04593-0-005
DVSS
DRVSS
HVSS OR RGVSS
Figure 4. Circuit 2. Digital Data Output
Figure 6. Circuit 4. H1 to H2, RG Drivers
Rev. A | Page 10 of 64
04593-0-007
AD9929
Table 8. Control Register Address Map
Address 0x00 0x01 Content (23:0) 23 (22:21) (20:18) 17 16 (15:14) 13 (12:10) (9:8) 7 6 5 4 (3:1) 0 0x02 (23:22) (21:16) (15:14) (13:8) (7:6) (5:0) (23:17) 16 (15:14) (13:8) (7:6) (5:0) (23:16) 15 (14:12) 11 (10:8) (7:3) (2:0) 0x05 (23:10) 9 8 (7:2) 1 0 Bit Width 24 1 2 3 1 1 2 1 3 2 1 1 1 1 3 1 2 6 2 6 2 6 7 1 2 6 2 6 8 1 3 1 3 5 3 14 1 1 6 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0x34 0 0x18 0 0x0B 0x00 0 0 0x00 0 0x10 0x80 - 5 0 5 0x00 2 0x0000 0 0 00 0 1 Default Value 000000 0 Register Name SW_RESET Unused XSUBCKSUPPRESS Unused HBLKMASK SYNCPOL Unused XSUBCKMODE_HP Unused MSHUTPAT MSHUT/VGATE_EN Unused CLPOB_CONT CLPOB_MODE Unused VDMODE Unused SHDLOC Unused SHPLOC DCLKPHASE DOUTPHASE Unused H1BLKRETIME Unused H1POSLOC Unused RGNEGLOC REFBLACK Unused H2DRV Unused H1DRV Unused RGDRV Unused AFESTBY DIGSTBY Unused OUTCONT_REG OUTCONT_ENB RG Drive Strength (0 = Off, 1 = 2.15 mA, 2 = 4.2 mA, 3 = 6.45 mA, 4 = 8.6 mA, 5 = 10.75 mA, 6 = 12.9 mA, 7 = 15.05 mA) AFE Standby (0 = Standby, 1 = Normal Operation) Digital Standby (0 = Standby, 1 = Normal Operation) Internal OUTCONT Signal Control (0 = Digital Outputs Held at Fixed DC Level, 1 = Normal Operation) External OUTCONT Signal Input Pin 43 Control (0 = Pin Enabled, 1 = Pin Disabled) H1 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA, 4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA) Selects MSHUT Pattern. (See Figure 51) (0 = Mshutpat0,1 = Mshutpat1,2 = Mshutpat2, 3 = Mshutpat3) MSHUT Masking of VGATE Input (0 = MSHUT Does Not Mask VGATE, 1 = MSHUT Does Mask VGATE) CLPOB Control (0 = CLPOB Off, 1 = CLPOB On) CLPOB CCD Region Control (See Table 19) VD Synchronous/Asynchronous Mode Setting (0 = VD Synchronous, 1 = VD Asynchronous ) SHD Sample Location SHP Sample Location DCLK Pulse Adjustment Data Output [11:0] Phase Adjustment Retimes the H1 HBLK to Internal Clock H1 Positive Edge Location RG Negative Edge Location Black Level Clamp H2 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA, 4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA) Register Description Software Reset = 000000 (Reset All Registers to Default ) Suppress XSUBCK (00 = No Suppression, 01 = Suppress First XSUBCK After Last VSG Line Pulse, 10 = Suppress All XSUBCKs, Except Final XSUBCK, 11 = No Suppression) Test Mode. Should Be Set = 0 Masking Polarity for H1 During Blanking Period (0 = Low, 1 = High) External SYNC Active Polarity (0 = Active Low) High Precision Shutter Mode Operation (0 = Single Pulse, 1 = Multiple Pulse)
0x03
0x04
Rev. A | Page 11 of 64
AD9929
Address 0x0A Content 23 22 (21:16) (15:12) (11:10) 9 8 (7:4) (3:2) 1 0 (23:22) 21 20 (19:17) 16 15 (14:12) 11 (10:0) (23:21) 20 (19:18) 17 16 15 (14:12) 11 (10:0) (23:17) 16 (15:11) (10:0) (23:22) (21:20) (19:18) 17 16 (15:10) (9:0) (23:8) (7:0) (23:13) (12:0) (23:13) (12:0) (23:13) (12:0) (23:13) (12:0) Bit Width 1 1 6 4 2 1 1 4 2 1 1 2 1 1 3 1 1 3 1 11 3 1 2 1 1 1 3 1 11 7 1 5 11 2 2 2 1 1 6 10 16 8 11 13 11 13 11 13 11 13 Default Value 0 0 0x00 0 0 0 0 C 3 0 0 0 1 1 0 0 0 0 0 0x7FF 0 0 0 0 0 0 0 0 0x000 - 0 - 0x000 0 0 0 0 0 0x00 0x000 0 60 - 0x1FFF - 0x1FFF - 0x1FFF - 0x1FFF Register Name Unused FDPOL XVSGMASK SYNCCNT SVREP_MODE HBLKEXT HPULSECNT SPATLOGIC SVOS SPAT_EN MODE Unused XSUBCK_EN XVSG_EN Unused STROBE_EN Unused XSUBCKNUM_HP Unused XSUBCKNUM Unused MSHUTINIT Unused Unused MSHUTEN Unused MSHUTPOS_HP Unused MSHUTPOS Unused VSUBPOL Unused VSUBTOG Unused TESTMODE1 Unused TESTMODE2 TESTMODE3 Unused VGAGAIN Unused XVSGLEN_1 Unused XV1SPAT_TOG1 Unused XV1SPAT_TOG2 Unused XV2SPAT_TOG1 Unused XV2SPAT_TOG2 Register Description FD Polarity Control (0 = Low, 1 = High) XVSG Masking (See Table 25) External SYNC Setting Super Vertical Repetition Mode H Pulse Blanking Extend Control H Pulse Control During Blanking SPAT Logic Setting (See Table 27) Second V Output Setting (10 = Ouput Repetition 1) SPAT Control (0 = SPAT Disable, 1 = SPAT Enable) Mode Control Bit (0 = Mode_A, 1 = Mode_B) XSUBCK Output Enable Control (0 = Disable, 1 = Enable) XVSG Output Enable Control (0 = Disable, 1 = Enable) STROBE Output Control (0 = STROBE Output Held Low, 1 = STROBE Output Enabled) High Precision Shutter XSUBCLK Pulse Position/Number Total Number of XSUBCKs Per Field MSHUT Initialize (1 = Forces MSHUT Low)
(VD SyncReg)1
0x0B
(VD SyncReg)1
0x0C
(VD SyncReg)1
MSHUT Control (0 = MSHUT Held at Last State, 1 = MSHUT Output) MSHUT Position during High Precision Operation MSHUT Position during Normal Operation VSUB Active Polarity (0 = Low, 1 = High) VSUB Toggle Position. Active Starting Line in any Field. This Register Should Always Be Set = 0. This Register Should Always Be Set = 0. This Register Should Always Be Set = 0. VGA Gain XVSGTOG_1 Pulse Width XV1SPAT Toggle Position #1 (Mode_A Active) XV1SPAT Toggle Position #2 (Mode_A Active) XV2SPAT Toggle Position #1 (Mode_A Active) XV2SPAT Toggle Position #2 (Mode_A active)
0x0D (VD SyncReg)1 0x0E
(VD SyncReg)1
0x0F 0x17 0x18 0x19 0x1A
Rev. A | Page 12 of 64
AD9929
Address 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0xD5 Content (23:13) (12:0) (23:13)) (12:0 (23:13) (12:0) (23:13) (12:0) (23:13) (12:0) (23:13) (12:0) (23:13) (12:0) (23:13) (12:0) (23:13) (12:0) (23:13) (12:0) (23:13) (12:0) (23:13) (12:0) (23:4) 3 2 0xD6 (1:0) (23:1) 0 Bit Width 11 13 11 13 11 13 11 13 11 13 11 13 11 13 11 13 11 13 11 13 11 13 11 13 20 1 1 2 23 1 Default Value - 0x1FFF - 0x1FFF - 0x1FFF - 0x1FFF - 0x1FFF - 0x1FFF - 0x1FFF - 0x1FFF - 0x1FFF - 0x1FFF - 0x1FFF - 0x1FFF 0x00000 1 0 0 0x000000 1 Register Name Unused XV3SPAT_TOG1 Unused XV3SPAT_TOG2 Unused XV4SPAT_TOG1 Unused XV4SPAT_TOG2 Unused XV1SPAT_TOG1 Unused XV1SPAT_TOG2 Unused XV2SPAT_TOG1 Unused XV2SPAT_TOG2 Unused XV3SPAT_TOG1 Unused XV3SPAT_TOG2 Unused XV4SPAT_TOG1 Unused XV4SPAT_TOG2 Unused DCLK2SEL DCLK1SEL CLKDIV Unused SLAVE_MODE Register Description XV3SPAT Toggle Position #1 (Mode_A active) XV3SPAT Toggle Position #2 (Mode_A active) XV4SPAT Toggle Position #1 (Mode_A active) XV4SPAT Toggle Position #2 (Mode_A Active) XV1SPAT Toggle Position #1 (Mode_A Active) XV1SPAT Toggle Position #2 (Mode_B Active) XV2SPAT Toggle Position #1 (Mode_B Active) XV2SPAT Toggle Position #2 (Mode_B Active) XV3SPAT Toggle Position #1 (Mode_B Active) XV3SPAT Toggle Position #2 (Mode_B Active) XV4SPAT Toggle Position #1 (Mode_B Active) XV4SPAT Toggle Position #2 (Mode_B Active) DCLK2 Selector (0 = Select Internal FD Signal To Be Output on FD/DCLK2 Pin 16, 1 = Select CLI To Be Output on FD/DCLK2 Pin 16) DCLK1 Selector (0 = Select DLL Version for DCLK1 Output, 1 = Select CLI for DCLK1 Output) Input Clock Divider (0 = No Division, 1 = 1/2, 2 = 1/3, 3 = 1/4) Operating Mode ( 0 = Master Mode, 1 = Slave Mode)
1
This register defaults to VD synchronous mode type at power-up. VD sync type registers do not get updated until the first falling edge of VD is asserted after the register has been programmed. VD sync type registers can be programmed to be asynchronous registers by setting VDMODE = 1 (Address 0x01).
Rev. A | Page 13 of 64
AD9929
Table 9. System Register Address Map (Address 0x14)
Register Sys_Reg(0) Content (31:24) (23:0) Sys_Reg(1) (31:23) 22 21 20 19 (18:10) (9:1) Sys_Reg(2) 0 (31:24) (23:15) (14:6) (5:0) (31:29) (28:20) (19:11) (10:2) 1 0 31 30 (29:21) (20:12) (11:3) (2:0) (31:26) (25:17) (16:8) (7:0) 31 (30:22) (21:13) 12 11 10 9 (8:0) (31:23) (22:14) (13:5) (4:0) (31:28) (27:19) (18:10) (9:1) 0 Bit Width 8 24 9 1 1 1 1 9 9 1 8 9 9 6 3 9 9 9 1 1 1 1 9 9 9 3 6 9 9 8 1 9 9 1 1 1 1 9 9 9 9 5 4 9 9 9 1 Default (Decimal) NA NA 37 0 0 1 1 0 19 0 12 31 0 19 12 31 104 0 0 1 1 18 58 47 96 0 76 38 105 57 0 0 1 1 0 29 19 48 0 29 19 48 - Register Name System_Reg_addr System_Number_N VTPLEN0 XV1STARTPOL0 XV2STARTPOL0 XV3STARTPOL0 XV4STARTPOL0 XV1TOG1POS0 XV1TOG2POS0 Vertical Sequence XV2TOG1POS0 [8] XV2TOG1POS0 [7:0] XV2TOG2POS0 XV3TOG1POS0 XV3TOG2POS0 [8:3] XV3TOG2POS0 [2:0] XV4TOG1POS0 XV4TOG2POS0 VTPLEN1 XV1STARTPOL1 XV2STARTPOL1 XV3STARTPOL1 XV4STARTPOL1 XV1TOG1POS1 XV1TOG2POS1 XV2TOG1POS1 XV2TOG2POS1 [8:6] XV2TOG2POS1 [5:0] XV3TOG1POS1 XV3TOG2POS1 XV4TOG1POS1 [8:1] XV4TOG1POS1 [0] XV4TOG2POS1 VTPLEN2 XV1STARTPOL2 XV2STARTPOL2 XV3STARTPOL2 XV4STARTPOL2 XV1TOG1POS2 XV1TOG2POS2 XV2TOG1POS2 XV2TOG2POS2 XV3TOG1POS2 [8:4] XV3TOG1POS2 [3:0] XV3TOG2POS2 XV4TOG1POS2 XV4TOG2POS2 Unused Register Description System Register Address is (Address 0x14) Number N Register Writes (0x000000 = Write All Registers) Vertical Sequence #0: Length Between Repetitions Vertical Sequence #0: XV1 Start Polarity Vertical Sequence #0: XV2 Start Polarity Vertical Sequence #0: XV3 Start Polarity Vertical Sequence #0: XV4 Start Polarity Vertical Sequence #0: XV1 Toggle Position 1 #0: XV1 Toggle Position 2 Vertical Sequence #0: XV2 Toggle Position 1 Vertical Sequence #0: XV2 Toggle Position 2 Vertical Sequence #0: XV3 Toggle Position 1 Vertical Sequence #0: XV3 Toggle Position 2 Vertical Sequence #0: XV4 Toggle Position 1 Vertical Sequence #0: XV4 Toggle Position 2 Vertical Sequence #1: Length Between Repetitions Vertical Sequence #1: XV1 Start Polarity Vertical Sequence #1: XV2 Start Polarity Vertical Sequence #1: XV3 Start Polarity Vertical Sequence #1: XV4 Start Polarity Vertical Sequence #1: XV1 Toggle Position 1 Vertical Sequence #1: XV1 Toggle Position 2 Vertical Sequence #1: XV2 Toggle Position 1 Vertical Sequence #1: XV2Toggle Position 2 Vertical Sequence #1: XV3 Toggle Position 1 Vertical Sequence #1: XV3 Toggle Position 2 Vertical Sequence #1: XV4 Toggle Position 1 Vertical Sequence #1: XV4 Toggle Position 2 Vertical Sequence #2: Length between Repetitions Vertical Sequence #2: XV1 Start Polarity Vertical Sequence #2: XV2 Start Polarity Vertical Sequence #2: XV3 Start Polarity Vertical Sequence #2: XV4 Start Polarity Vertical Sequence #2: XV1 Toggle Position 1 Vertical Sequence #2: XV1 Toggle Position 2 Vertical Sequence #2: XV2 Toggle Position 1 Vertical Sequence #2: XV2 Toggle Position 2 Vertical Sequence #2: XV3 Toggle Position 1 Vertical Sequence #2: XV3 Toggle Position 2 Vertical Sequence #2: XV4 Toggle Position 1 Vertical Sequence #2: XV4 Toggle Position 2
Sys_Reg(3)
Sys_Reg(4)
Sys_Reg(5)
Sys_Reg(6)
Sys_Reg(7)
Sys_Reg(8)
Rev. A | Page 14 of 64
AD9929
Register Sys_Reg(9) Content (31:23) 22 21 20 19 (18:10) (9:1) 0 (31:24) (23:15) (14:6) (5:0) (31:29) (28:20) (19:11) (10:1) 0 (31:20) (19:10) (9:1) 0 (31:24) (23:16) (15:5) (4:0) (31:26) (25:18) (17:9) (8:0) (31:23) (22:14:) (13:2) (1:0) (31:22) (21:18) (17:8) (7:0) Bit Width 9 1 1 1 1 9 9 1 8 9 9 6 3 9 9 10 1 12 10 9 1 8 8 11 5 6 8 9 9 9 9 12 2 10 4 10 8 Default (Decimal) 89 0 0 1 1 0 60 30 90 0 60 30 90 0 - 2283 130 100 0 118 1048 1198 60 19 88 19 88 2243 2278 9 120 - Register Name VTPLEN3 XV1STARTPOL3 XV2STARTPOL3 XV3STARTPOL3 XV4STARTPOL3 XV1TOG1POS3 XV1TOG2POS3 XV2TOG1POS3 [8] XV2TOG1POS3 [7:0] XV2TOG2POS3 XV3TOG1POS3 XV3TOG2POS3 [8:3] XV3TOG2POS3 [2:0] XV4TOG1POS3 XV4TOG2POS3 HBLKHPOS Unused HDLEN1 HLEN OLEN BLLEN [8] BLLEN [7:0] MSHUTLEN XVSGTOG_0 XVSGTOG_1 [10:6] XVSGTOG_1 [5:0] XVSGLEN_0 XSUBCK1TOG1 XSUBCK1TOG2 XSUBCK2TOG1 XSUBCK2TOG2 CLPTOG11 CLPTOG2 [11]1 CLPTOG2 [10:0] 1 VDRISE HDRISE Unused Register Description Vertical Sequence #3: Length Between Repetitions Vertical Sequence #3: XV1 Start Polarity Vertical Sequence #3: XV2 Start Polarity Vertical Sequence #3: XV3 Start Polarity Vertical Sequence #3: XV4 Start Polarity Vertical Sequence #3: XV1 Toggle Position 1 Vertical Sequence #3: XV1 Toggle Position 2 Vertical Sequence #3: XV2 Toggle Position 1 Vertical Sequence #3: XV2 Toggle Position 2 Vertical Sequence #3: XV3 Toggle Position 1 Vertical Sequence #3: XV3 Toggle Position 2 Vertical Sequence #3: XV4 Toggle Position 1 Vertical Sequence #3: XV4 Toggle Position 2 H1 Pulse ON Position during Blanking Period 12-bit Gray Code HD Counter Value (Gray Code Number) 10-Bit HL Counter Values 9-Bit OL Counter Value 9-bit BL Counter Value MSHUT Sequence Length XVSGTOG_0 Toggle Position XVSG TOG_1 Toggle Position XVSGTOG_0 Pulse Width XSUBCK1 1st Toggle Position XSUBCK1 2nd Toggle Position XSUBCK2 1st Toggle Position XSUBCK2 2nd Toggle Position CLPOB Toggle Position 1 (Gray Code Number) CLPOB Toggle Position 2 (Gray Code Number) VD Toggle Position 1 HD Toggle Position 2
Sys_Reg(10)
Sys_Reg(11)
Sys_Reg(12)
Sys_Reg(13)
Sys_Reg(14)
Sys_Reg(15)
Sys_Reg(16)
1
Register value must be a gray code number (see Gray Code Registers section).
Rev. A | Page 15 of 64
AD9929
Table 10. Mode_A Register Map (Address 0x15)
Register Mode_Reg(0) Mode_Reg(1) Content (31:24) (23:0) (31:21) (20:9) 8 7 (6:0) 31 (30:28) (27:25) (24:22) (21:19) (18:16) 15 14 13 12 11 (10:3) (2:0) (31:27) (26:19) (18:11) (10:9) (8:7) (6:5) (4:3) (2:0) (31:29) (28:26) (25:23) (22:12) (11:1) 0 (31:19) (18:6) (5:0) (31:25) (24:12) (11:0) 31 (30:18) (17:5) (4:0) (31:24) (23:11) (10:9) (8:0) Bit Width 8 24 11 12 1 1 7 1 3 3 3 3 3 1 1 1 1 1 8 3 5 8 8 2 2 2 2 3 3 3 3 11 11 1 13 13 6 7 13 12 1 13 13 5 8 13 2 9 Default (Decimal) NA NA 262 1139 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 - 988 1138 1078 1168 958 1138 988 1228 1392 3 - Register Name Mode_A_addr Mode_A_Number_N VDLEN HDLASTLEN1 XVSGSEL1 XVSGSEL2 XVSGACTLINE SUBCKSEL VTPSEQPTR0 VTPSEQPTR1 VTPSEQPTR2 VTPSEQPTR3 VTPSEQPTR4 CLPEN0 CLPEN1 CLPEN2 CLPEN3 CLPEN4 SCP1 SCP2 SCP2 SCP3 SCP4 VTPSEL0 VTPSEL1 VTPSEL2 VTPSEL3 VTPREP0 VTPREP1 VTPREP2 VTPREP3 SVREP0 SVREP3 Unused XV1SPAT_TOG3 XV1SPAT_TOG4 XV2SPAT_TOG3 XV2SPAT_TOG3 XV2SPAT_TOG XV3SPAT_TOG3 XV3SPAT_TOG3 XV3SPAT_TOG4 XV4SPAT_TOG3 XV4SPAT_TOG4 XV4SPAT_TOG4 SECONDVPOS VPATSECOND Unused Register Description Mode_A Address Is (Address 0x15) Number N Register Writes (0x000000 = Write All Registers ) VD Counter Value Number of Pixels in Last Line (Gray Code Number) XVSG1 Sequence Selector (See Table 35) XVSG2 Sequence Selector (See Table 35) XVSG Active Line Select one of two SUBCK patterns Vertical Transfer Sequence Region 0 Vertical Transfer Sequence Region 1 Vertical Transfer Sequence Region 2 Vertical Transfer Sequence Region 3 Vertical Transfer Sequence Region 4 CLPOB Output Control 1 CLPOB Output Control 2 CLPOB Output Control 3 CLPOB Output Control 4 CLPOB Output Control 5 Sequence Change Position 1 Sequence Change Position 2 Sequence Change Position 3 Sequence Change Position 4 Vertical Pattern Selection 0 Vertical Pattern Selection 1 Vertical Pattern Selection 2 Vertical Pattern Selection 3 Number of Vertical Pulse Repetitions for Pattern 0 Number of Vertical Pulse Repetitions for Pattern 1 Number of Vertical Pulse Repetitions for Pattern 2 Number of Vertical Pulse Repetitions for Pattern 3 Vertical Sweep Repetition Number for CCD Region 0 Vertical Sweep Repetition Number for CCD Region 3 XV1SPAT Toggle Position 3 XV1SPAT Toggle Position 4 XV2SPAT Toggle Position 3 XV2SPAT Toggle Position 4 XV3SPAT Toggle Position 3 XV3SPAT Toggle Position 4 XV4SPAT Toggle Position 3 XV4SPAT Toggle Position 4 Second V Pattern Output Position Selected Second V-Pattern Group for VSG Active Line
Mode_Reg(2)
Mode_Reg(3)
Mode_Reg(4)
Mode_Reg(5)
Mode_Reg(6)
Mode_Reg(7)
Mode_Reg(8)
1
Register value must be a gray code number (see Gray Code Registers section).
Rev. A | Page 16 of 64
AD9929
Table 11. Mode_B Register Map (Address 0x16)
Register Mode_Reg(0) Mode_Reg(1) Content (31:24) (23:0) (31:21) (20:9) 8 7 (6:0) 31 (30:28) (27:25) (24:22) (21:19) (18:16) 15 14 13 12 11 (10:3) (2:0) (31:27) (26:19) (18:11) (10:9) (8:7) (6:5) (4:3) (2:0) (31:29) (28:26) (25:23) (22:12) (11:1) 0 (31:19) (18:6) (5:0) (31:25) (24:12) (11:0) 31 (30:18) (17:5) (4:0) (31:24) (23:11) (10:9) (8:0) Bit Width 8 24 11 12 1 1 7 1 3 3 3 3 3 1 1 1 1 1 8 3 5 8 8 2 2 2 2 3 3 3 3 11 11 1 13 13 6 7 13 12 1 13 13 5 8 13 2 9 Default (Decimal) NA NA 262 1139 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 - 988 1138 1078 Register Name Mode_B_addr Mode_B_Number_N VDLEN HDLASTLEN1 XVSGSEL1 XVSGSEL2 XVSGACTLINE SUBCKSEL VTPSEQPTR0 VTPSEQPTR1 VTPSEQPTR2 VTPSEQPTR3 VTPSEQPTR4 CLPEN0 CLPEN1 CLPEN2 CLPEN3 CLPEN4 SCP1 SCP2 SCP2 SCP3 SCP4 VTPSEL0 VTPSEL1 VTPSEL2 VTPSEL3 VTPREP0 VTPREP1 VTPREP2 VTPREP3 SVREP0 SVREP3 Unused XV1SPAT_TOG3 XV1SPAT_TOG4 XV2SPAT_TOG3 XV2SPAT_TOG3 XV2SPAT_TOG4 XV3SPAT_TOG3 XV3SPAT_TOG3 XV3SPAT_TOG4 XV4SPAT_TOG3 XV4SPAT_TOG4 XV4SPAT_TOG4 SECONDVPOS VPATSECOND Unused Register Description Mode_B Address is (Address 0x16) Number N Register Writes (0x000000 = Write All Registers) VD Counter Value Number of Pixels in Last Line (Gray Code Number) XVSG1 Sequence Selector (See Table 35) XVSG2 Sequence Selector (See Table 35) XVSG Active Line Select One of Two SUBCK Patterns Vertical Transfer Sequence Region 0 Vertical Transfer Sequence Region 1 Vertical Transfer Sequence Region 2 Vertical Transfer Sequence Region 3 Vertical Transfer Sequence Region 4 CLPOB Output Control 1 CLPOB Output Control 2 CLPOB Output Control 3 CLPOB Output Control 4 CLPOB Output Control 5 Sequence Change Position 1 Sequence Change Position 2 Sequence Change Position 3 Sequence Change Position 4 Vertical Pattern Selection 0 Vertical Pattern Selection 1 Vertical Pattern Selection 2 Vertical Pattern Selection 3 Number of VTP0 Pulse Repetitions for Pattern 0 Number of VTP1 Pulse Repetitions for Pattern 1 Number of VTP2 Pulse Repetitions for Pattern 2 Number of VTP0 Pulse Repetitions for Pattern 3 Vertical Sweep Repetition Number for CCD Region 0 Vertical Sweep Repetition Number for CCD Region 3 XV1SPAT Toggle Position 3 XV1SPAT Toggle Position 4 XV2SPAT Toggle Position 3 XV2SPAT Toggle Position 4 XV3SPAT Toggle Position 3 XV3SPAT Toggle Position 4 XV4SPAT Toggle Position 3 XV4SPAT Toggle Position 4 Second V Pattern Output Position Selected Second V-Pattern Group for VSG Active Line
Mode_Reg(2)
Mode_Reg(3)
Mode_Reg(4)
Mode_Reg(5)
Mode_Reg(6)
Mode_Reg(7)
958 1138 988 1228 1392 3 -
Mode_Reg(8)
1
Register value must be a gray code number (See Gray Code Registers section). Rev. A | Page 17 of 64
AD9929 SYSTEM OVERVIEW
Figure 7 shows the typical system block diagram for the AD9929. The CCD output is processed by the AD9929's AFE circuitry, which consists of a CDS, VGA, black level clamp, and an A/D converter. The digitized pixel information is sent to the digital image processor chip, which performs post-processing and compression. To operate the CCD, all CCD timing parameters are programmed into the AD9929 from the system microprocessor through the 3-wire serial interface. From the system master clock, CLI, provided by the image processor or external crystal, the AD9929 generates all of the CCDs horizontal and vertical clocks and all internal AFE clocks. External synchronization is provided by a SYNC pulse from the microprocessor, which resets internal counters and resynchronizes the VD and HD outputs. The H-drivers for H1 to H2, and RG are included in the AD9929, allowing these clocks to be directly connected to the CCD. An H-drive voltage of up to 3.6 V is supported. The AD9929 also includes the CCD vertical driver circuits for creating the V1 to V4, and SUBCK outputs that allow direct connection to the CCD. The AD9929 also provides programmable MSHUT and STROBE outputs, which may be used to trigger mechanical shutter and strobe (flash) circuitry.
CCDIN CCD V1 V2 V3 V4 VERTICAL DRIVER
AD9929
XV1 XV2 XV3 XV4 XVSG1 TIMING GENERATOR DOUT [11:0] DCLK1 FD HD, VD VGATE CLI DIGITAL IMAGE PROCESSING ASIC
SUBCK
XVSG2 XSUBCK
H1 H2 RG VSUB
SERIAL INTERFACE
SYNC
OUTCONT
MSHUT
STROBE
P
Figure 7. Typical System Block Diagram, Master Mode
Rev. A | Page 18 of 64
04593-0-008
AD9929 THEORY OF OPERATION
MODES OF OPERATION
Slave and Master Mode Operation
The AD9929 can be operated in either slave or master mode. It defaults to slave mode operation at power-up. The SLAVE_MODE register (Address 0xD6) can be used to configure the AD9929 into master mode by setting SLAVE_MODE = 0.
11-BIT VERTICAL COUNTER = 2048 LINES MAX
MAXIMUM FIELD DIMENSIONS
12-BIT HORIZONTAL COUNTER = 4096 PIXELS MAX
Slave Mode Operation
While operating in slave mode, VD, HD, and VGATE are provided externally from the image processor. VGATE is input active high on Pin 45. Unlike master mode operation, there is a 7 CLI clock cycle delay from the falling edge of HD to when the 12-bit gray code H counter is reset to 0 (See Figure 62).
Figure 8. Horizontal and Vertical Counters
Master Mode Operation
While operating in master mode, VD and HD are outputs and the SYNC/VGATE pin is configured for an external SYNC input. Master mode is selected by setting register SLAVE_MODE (Address 0x06) = 0.
GRAY CODE REGISTERS
See Table 12 for a list of the AD9929 registers requiring gray code values. The following is an example of applying a gray code number for HDLEN using a line length of 1560 pixels: HDLEN = (1560-4) = 155610 (see Special Note about the HDLEN Register section). Where 155610 = Address 0x51E The gray code value of Address 0x51E would be programmed in the 12-bit HDLEN register. Table 12. AD9929 Gray Code Registers
Register Name HDLEN CLPOBTOG1 CLPOBTOG2 HDLASTLEN Register Type System_Reg(12) System_Reg(15) System_Reg(16) Mode_Reg(1)
HORIZONTAL AND VERTICAL COUNTERS
Figure 8 and Figure 9 show the horizontal and vertical counter dimensions for the AD9929. All internal horizontal and vertical clocking is programmed using these dimensions to specify line and pixel locations.
CLI INPUT CLOCK DIVIDER
The AD9929 provides the capability of dividing the CLI input clock using Register CLKDIV (Address 0xD5). The following procedure must be followed to reset the AFE and digital circuits when CLKDIV is reprogrammed back to 0 from CLKDIV = 1, 2, or 3. The DCLK1 output becomes unstable if this procedure isn't followed. Step 1: CLKDIV = 1, 2, or 3 (CLI divided by setting value) Step 2: CLKDIV = 0 (CLI reprogrammed for no division) Step 3: DIGSTBY = AFESTBY = 0 Step 4: DIGSTBY = AFESTBY = 1
MAX VD LENGTH IS 2048 LINES
VD
MAX HD LENGTH IS 4095 PIXELS
HD
Figure 9. Maximum VD/HD Dimensions
Rev. A | Page 19 of 64
04593-0-010
CLI
04593-0-009
AD9929
SERIAL INTERFACE TIMING
All of the internal registers of the AD9929 are accessed through a 3-wire serial interface. The 3-wire interface consists of a clock (SCK), serial load (SL), and serial data (SDATA). The AD9929 has three different register types that are configured by the 3-wire serial interface. As described in Table 13, the three register types are control registers, system registers, and mode registers. Table 13. Types of Serial Interface Registers
Register Control System Mode_A Mode_B Address 0x00 to 0xD6 0x14 0x15 0x16 Number of Registers 24-Bit Registers at Each Address. Not All Addresses Are Used. See Table 8. Seventeen 32-Bit System Registers at Address 0x14. See Table 9. Eight 32-bit Mode_A Registers at Address 0x15. See Table 10. Eight 32-Bit Mode_B Registers at Address 0x16. See Table 11.
writing to the system registers, SDATA contains the 8-bit Address 0x14, followed by Number Writes N [23:0], followed by the Sys_Reg [31:0] data, as shown in Figure 5. The system register map is listed in Table 9. The value of the Number Writes N [23:0] word determines one of two options when writing to the system registers. If Number Writes N[23:0] = 0x000000, the device enters a mode where it expects all 17 Sys_Reg [31:0] data-words to be clocked in before SL is asserted high. If the Number Writes N [23:0] is decoded as some number N other than 0x000000, then the device expects N number of registers to be programmed, where N equals the value of Number Writes N [23:0]. For example: if Number Writes N[23:0] = 0x000004, the device would expect data to be provided for Sys_Reg [3:0]. In all cases, the system registers are written beginning with Sys_Reg [0], regardless of the value of Number Writes N [23:0]. Note that SL can be brought high or low during access to system registers, as shown in Figure 11. Mode_A and Mode_B Register Serial Interface There are eight 32-bit Mode_A and eight 32-bit Mode_B registers that get accessed sequentially at Address 0x15 and Address 0x16, respectively. Mode_A and Mode_B registers are written to in exactly the same way as the system registers, as explained previously. The mode registers are listed in Table 10 and Table 11. To change operation between Mode_A and Mode_B, set the 1-bit mode register (Address 0x0A). The desired Mode_A (Address 0x15) or Mode_B (Address 0x16) data must be programmed into the Mode_A or Mode_B registers before changing the mode bit.
Registers
Control Register Serial Interface The control register 3-wire interface timing requirements are shown in Figure 10. Control data must be written into the device one address at a time due to the noncontiguous address spacing for the control registers. This requires writing 8 bits of address data followed by 24 bits of configuration data between each active low period of SL for each address. The SL signal must be kept high for at least one full SCK cycle between successive writes to control registers. System Register Serial Interface There are seventeen 32-bit system registers that are accessed sequentially at Address 0x14, beginning with Sys_Reg [0]. When
SDATA
A7
A6
A5
A4
A3
A2
A1
A0
D23
D22
D21
....
D3
D2
D1
D0
tDS
SCK 1
tDH
.... 2 3 4 5 6 7 8 9 10 11 29 30 31 32
tLS
SL NOTES 1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK. 2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE. 3. THIS TIMING PATTERN MUST BE WRITTEN FOR EACH REGISTER WRITE WITH SL REMAINING HIGH FOR AT LEAST ONE FULL SCK PERIOD BEFORE ASSERTING SL LOW AGAIN FOR THE NEXT REGISTER WRITE.
tLH
Figure 10. 3-Wire Serial Interface Timing for Control Registers
Rev. A | Page 20 of 64
04593-0-011
AD9929
ADDRESS [7:0] NUMBER WRITES N [23:0] DATA 1 [31:0] DATA 2 [31:0] DATA N [31:0]
D2 D1 D0 D31
N23
N22 N21
N20
N1 N0 D31
D30 D29
D30 D29
D31
D3
D2 D1 D0
D3
8 BIT ADDRESS
NUMBER OF 32 BIT DATA WRITES (N)
DATA 1 [31:0]
DATA 2 [31:0]
DATA N [31:0]
SCK
SL
1
1
12
D2 D1 D0
04539-0-013
SDATA
D30 D29
A7 A6 A5
A4 A3 A2
A1 A0
N3
N2
D3
NOTES 1. SL PULSES ARE IGNORED UNTIL THE LSB BIT OF THE LAST DATA N WORD IS CLOCKED IN. 2. VALID SL PULSE. SL MUST BE ASSERTED HIGH WHEN ALL SDI DATA TRANSMISSIONS HAVE BEEN FINISHED.
Figure 11. System and Mode Register Writes
OPERATION OF VD SYNCHRONOUS TYPE REGISTER WRITES BEGIN AT THE NEXT VD FALLING EDGE.
VD
HD
CLI
PROGRAMMING VD SYNCHRONOUS TYPE REGISTERS MUST BE COMPLETED AT LEAST 4 CLI CYCLES BEFORE THE FALLING EDGE OF VD
Figure 12. VD Synchronous Type Register Writes
VD Synchronous and Asynchronous Register Operation There are two types of control registers, VD synchronous and VD asynchronous, as indicated in the address column of Table 8. Register writes to synchronous and asynchronous registers operate differently, as described in the following sections. All writes to system Mode_A and Mode_B registers occur asynchronously. Asynchronous Register Operation For VD asynchronous register writes, SDATA data is stored directly into the serial register at the rising edge of SL. As a result, register operation begins immediately after the rising edge of SL.
VD Synchronous Register Operation For VD synchronous registers, SDATA data is temporarily stored in a buffer register at the rising edge of SL. This data is held in the buffer register until the next falling edge of VD is applied. Once the next falling edge of VD occurs, the buffered SDATA data is loaded into the serial register, at which time the register operation begins. See Figure 12. All control registers at the following addresses are VD synchronous type registers: Addresses 0x0A, 0x0B, 0x0C, 0x0D, and 0x0E. Also see Table 8, the Control Register Address Map.
Rev. A | Page 21 of 64
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AD9929
ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9929 AFE signal processing chain is shown in Figure 13. Each processing step is essential in achieving a high quality image from the raw CCD pixel data. Registers for the AD9929 AFE section are listed in Table 14. Table 14. AFE Registers
Register Name VGAGAIN REFBLACK AFESTBY Bit Width 10 6 1 Register Type Control (Address 0x0E) Control (Address 0x04) Control (Address 0x05) Description VGA Gain Black Clamp Level AFE Standby
DC Restore
To reduce the large dc offset of the CCD output signal, a dcrestore circuit is used with an external 0.1 F series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.5 V, to be compatible with the 3 V analog supply of the AD9929.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the video information and reject low frequency noise. The timing shown in Figure 16 illustrates how the two internally generated CDS clocks, SHP and SHD, are used to sample the reference and data levels, respectively, of the CCD signal. The placement of the SHP and SHD sampling edges is determined by the setting of the SHPLOC (Address 0x02) and SHDLOC (Address 0x02) registers. Placement of these two clock edges is critical in achieving the best performance from the CCD.
1.0F REFB DC RESTORE 1.5V SHP SHD 6dB TO 40dB 0.1F CCDIN CDS VGA 1.0V INTERNAL VREF 2V FULL SCALE
1.0F REFT 2.0V
DOUT PHASE
ADC
OUTPUT DATA LATCH
12 DOUT
10 VGA GAIN REGISTER 8-BIT DAC
OPTICAL BLACK CLAMP CLPOB DIGITAL FILTER
8
SHP DOUT SHD PHASE CLPOB CLAMP LEVEL REGISTER
Figure 13. AFE Block Diagram
Rev. A | Page 22 of 64
04593-0-014
PRECISION TIMING GENERATION
V-H TIMING GENERATION
AD9929
Variable Gain Amplifier
The VGA provides a gain range of 6 dB to 40 dB, programmable with 10-bit resolution through the serial digital interface. The minimum gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. The VGA gain curve follows a "linear-in-dB" characteristic. The exact VGA gain can be calculated for any gain register value by using the equation Gain = (0.035 x Code) + 5.2 where the code range is 0 to 1023. Figure 14 shows a typical AD9929 VGA gain curve.
42
A/D Converter
The AD9929 uses high-performance 12-bit ADC architecture, optimized for high speed and low power. Differential Nonlinearity (DNL) performance is typically better than 0.5 LSB. The ADC uses a 2 V input range. Better noise performance results from using a larger ADC full-scale range.
PRECISION TIMING, HIGH SPEED TIMING GENERATION
The AD9929 generates flexible, high speed timing signals using the precision timing core. This core is the foundation for generating the timing used for both the CCD and the AFE: the reset gate RG, horizontal drivers H1 to H2, and the CDS sample clocks. A unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal CCD readout and the AFE correlated double sampling.
36
VGA GAIN (dB)
30
Timing Resolution
The precision timing core uses the master clock input (CLI) as a reference. This clock should be the same as the CCD pixel clock frequency. Figure 15 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. Using a 36 MHz CLI frequency, the edge resolution of the precision timing core is 0.58 ns. A 72 MHz CLI frequency can be applied to the AD9929, where the AD9929 will internally divide the CLI frequency by two. Division by 1/3 and 1/4 are also provided. CLI frequency division is controlled by using CLKDIV (Address 0x05) register.
24
18
12
6 0 127 255 383 511 639 767 895 1023 VGA GAIN REGISTER CODE
Figure 14. VGA Gain Curve
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD's black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with a fixed black level reference selected by the user in the clamp level register. Any value between 0 LSB and 255 LSB may be programmed with 8-bit resolution. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input through a D/A converter. Normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. The optical black clamp is controlled by the CLPOB signal, which is fully programmable (see Horizontal Clamping and Blanking section). System timing examples are shown in the Horizontal and Vertical Synchronous Timing section. The CLPOB pulse should be placed during the CCDs optical black pixels. It is recommended that the CLPOB pulse duration be at least 20 pixels wide. Shorter pulse widths may be used, but the ability to track low frequency variations in the black level is reduced.
04593-0-015
High Speed Clock Programmability
Figure 17 shows how the high speed clocks RG, H1 to H2, SHP, and SHD are generated. The RG pulse has a fixed rising edge and a programmable falling edge. The horizontal clock H1 has a programmable rising and a fixed falling edge occurring at H1POSLOC + 24 steps. The H2 clock is always the inverse of H1. Table 14 summarizes the high speed timing registers and the parameters for the high speed clocks. Each register is 6 bits wide with the 2 MSB bits used to select the quadrant region, as outlined in Table 16. Figure 17 shows the range and default locations of the high speed clock signals.
H DRIVER AND RG OUTPUTS
In addition to the programmable timing positions, the AD9929 features on-chip output drivers for the RG and H1 to H2 outputs. These drivers are powerful enough to directly drive the CCD inputs. The H-driver current can be adjusted for optimum rise/fall time into a particular load by using the H1DRV and H2DRV registers (Address 0x04). The RG drive current is adjustable using the RGDRV register (Address 0x04). The H1DRV and H2DRV register is adjustable in 4.3 mA increments. The RGDRV register is adjustable in 2.15 mA increments. All DRV registers have settings of 0 equal to OFF or three-state, and a maximum setting of 7.
Rev. A | Page 23 of 64
AD9929
As shown in Figure 17, the H2 output is the inverse of H1. The internal propagation delay resulting from the signal inversion is less than 1 ns, which is significantly less than the typical rise time driving the CCD load. This results in a H1/H2 crossover voltage at approximately 50% of the output swing. The crossover voltage is not programmable.
POSITION CLI
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
tCLIDLY
1 PIXEL PERIOD
NOTES 1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS. 2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6ns TYP).
Figure 15. High Speed Clock Resolution from CLI Master Clock Input
3 CCD SIGNAL 4
CDS (INTERNAL) 1 RG 2
5 H1
6
H2
PROGRAMMABLE CLOCK POSITIONS 1. RG RISING EDGE (FIXED EDGE AT 000000) 2. RG FALLING EDGE (RGNEGLOC (ADDRESS 0x03)) 3. SHP SAMPLE LOCATION (SHPLOC (ADDRESS 0x02)) 4. SHD SAMPLE LOCATION (SHDLOC (ADDRESS 0x02)) 5. H1 RISING EDGE LOCATION (H1POSLOC (ADDRESS 0x03)) 6. H1 NEGATIVE EDGE LOCATION (FIXED AT (H1POSLOC + 24 STEPS)) 7. H2 IS ALWAYS THE INVERSE OF H1
Figure 16. High Speed Clock Programmable Locations
Table 15. RG, H1, SHP, SHD, DCLK, and DOUTPHASE Timing Parameters
Register Name RGNEGLOC1 H1POSLOC1 SHPLOC1 SHDLOC1 DOUTPHASE1 DCLKPHASE Bit Width 6b 6b 6b 6b 6b 6b Register Type Control (Address 0x03) Control (Address 0x03) Control (Address 0x02) Control (Address 0x02) Control (Address 0x02) Control (Address 0x02) Range 0 to 47 Edge Location 0 to 47 Edge Location 0 to 47 Edge Location 0 to 47 Edge Location 0 to 47 Edge Location 0 to 47 Edge Location Description Falling Edge Location for RG Positive Edge Location for H1 Sample Location for SHP Sample Location for SHD Phase Location of Data Output [9:0] Positive Edge of DCLK 1
1
The two MSB bits are used to select the quadrant
Rev. A | Page 24 of 64
04593-0-017
04593-0-016
AD9929
Table 16. Precision Timing Edge Locations for RG, H1, SHP, SHD, DCLK, and DOUTPHASE
Signal Name RG Quadrant I II III IV RG Rising Edge (Not Programmable) fixed at 000000 fixed at 000000 fixed at 000000 fixed at 000000 RGNEGLOC 000000 to 001011 010000 to 011011 100000 to 101011 RG Falling Edge Quadrant Range P[0] to P[11] P[12] to P[23] P[24] to P[35] P[36] to P[47] H1 Falling Edge (Not Programmable) H1POSLOC + 24 Steps H1POSLOC + 24 Steps H1POSLOC + 24 Steps H1POSLOC + 24 Steps
Signal Name H1
Quadrant I II III IV
H1POSLOC 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011
H1 Rising Edge Quadrant Range P[0] to P[11] P[12] to P[23] P[24] to P[35] P[36] to P[47]
Signal Name CDS
Quadrant I II III IV
CDS Rising Edge SHPLOC Quadrant Range P[0] to P[11] 000000 to 001011 P[12] to P[23] 010000 to 011011 P[24] to P[35] 100000 to 101011 P[36] to P[47] 110000 to 111011
CDS Falling Edge SHDLOC Quadrant Range P[0] to P[11] 000000 to 001011 P[12] to P[23] 010000 to 011011 P[24] to P[35] 100000 to 101011 P[36] to P[47] 110000 to 111011 Data Output[9:0] Falling Edge (Not Programmable) DOUTPHASE + 24 Steps DOUTPHASE + 24 Steps DOUTPHASE + 24 Steps DOUTPHASE + 24 Steps DCLKPHASE Falling Edge P[26] P[36] P[06] P[16]
Signal Name Data Output [9:0]
Quadrant I II III IV
Data Output[9:0] Rising Edge DOUTPHASE Quadrant Range P[0] to P[11] 000000 to 001011 P[12] to P[23] 010000 to 011011 P[24] to P[35] 100000 to 101011 P[36] to P[47] 110000 to 111011 DCLK PHASE Rising Edge P[6] P[16] P[26] P[36]
Signal Name DCLK1
DCLKPHASE Value 00 01 10 11
Rev. A | Page 25 of 64
AD9929
POSITION P[0] P[12] P[24] P[36] P[48] = P[0]
PIXEL PERIOD RGr[0] RG RGf[12]
Hr[0] H1
Hf[24]
CDS (INTERNAL)
tS1
SHP[20] CCD SIGNAL SHD[40]
NOTES 1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. 2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.
Figure 17. High Speed Clock Default and Programmable Locations
tRISE
H1 H2
tPD < tRISE tPD
H1 FIXED CROSSOVER VOLTAGE H2
04593-0-019
Figure 18. H-Clock Inverse Phase Relationship
P[0] P[12] P[24] P[36] P[48] = P[0]
PIXEL PERIOD
DCLK1
tOD
DOUT
NOTES 1. DCLK1 PHASE IS ADJUSTED BY SETTING THE DCLKPHASE REGISTER (ADDRESS 0x02) 2. DOUT PHASE CAN BE ADJUSTED BY SETTING THE DOUTPHASE REGISTER (ADDRESS 0x02)
Figure 19. Digital Output Phase Adjustment
DIGITAL DATA OUTPUTS
The AD9929 DOUT[11:0] and DCLK phases are independently programmable using the DOUTPHASE register (Address 0x02) and DCLKPHASE register (Address 0x02). Refer to Figure 19.
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04593-0-018
AD9929 EXTERNAL SYNCHRONIZATION (MASTER MODE)
External synchronization can be applied to synchronize the VD and HD signals by applying an external pulse on the SYNC/GATE (Pin 45) pin for master mode operation. The SYNC/GATE pin is configured as an external SYNC input for master mode operation by setting the SLAVE_MODE register (Address 0xD6) = 0 (the AD9929 defaults to slave mode at power-up). SYNCCNT (Address 0x0A) and SYNCPOL (Address 0x01) are the only two registers used for configuring the AD9929 for external synchronization. The SYNCPOL is a 1-bit register used for configuring the SYNC input as either active low or active high. The AD9929 defaults to active low at power-up. The function of the SYNCCNT register is described in Table 17. Figure 20 and Figure 21 provide two examples of external synchronization with SYNCPOL = 0. Table 17. External Synchronization (Master Mode)
SYNCCNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
4 CLI
External Synchronization Options Disable External Synchronization VD Sync at every SYNC Pulse VD Sync after 2nd Applied SYNC Pulse VD Sync after 3rd Applied SYNC Pulse VD Sync after 4th Applied SYNC Pulse VD Sync after 5th Applied SYNC Pulse VD Sync after 6th Applied SYNC Pulse VD Sync after 7th Applied SYNC Pulse VD Sync after 8th Applied SYNC Pulse VD Sync after 9th Applied SYNC Pulse VD Sync after 10th Applied SYNC Pulse VD Sync after 11th Applied SYNC Pulse VD Sync after 12th Applied SYNC Pulse VD Sync after 13th Applied SYNC Pulse VD Sync after 14th Applied SYNC Pulse VD Sync after 1st Applied SYNC Pulse Only
4 CLI
4 CLI VD
SYNC 2 CLIMIN CHANGE TO MODE B SERIAL WRITES
04593-0-021
04593-0-022
OPERATION MODE
MODE A
MODE B
Figure 20. Example of Synchronization with SYNCPOL = 0 and SYNCCNT = 1
4 CLI VD
4 CLI
4 CLI
SYNC 2 CLIMIN
Figure 21. Example of Synchronization with SYNCPOL = 0 and CYNCCNT = 3
Rev. A | Page 27 of 64
AD9929 HORIZONTAL AND VERTICAL SYNCHRONOUS TIMING
The HD and VD output pulses are programmable using the registers listed in Table 18. The HD output is asserted low at the start of the horizontal line shift. The VD output is asserted low at the start of each line. As shown in Figure 22, the 11-bit VD counter is used to count the number of lines set by the VDLEN register. The 12-bit HD counter is used to count the number of pixels in each line set by the HDLEN register. For example, if the CCD array size is 2000 lines by 2100 pixels per line, VDLEN = 2000 and HDLEN = 0xC28. The HDLEN register sets HL as a reference for the rising edge of the HD pulse. Table 18. HD and VD Registers
Register Name HDLEN1 HLEN HDRISE HDLASTLEN1 VDLEN VDRISE Bit Width 12 10 10 12 11 4 Register Type Sys_Reg(12) Sys_Reg(12) Sys_Reg(16) Mode_Reg(1) Mode_Reg(1) Sys_Reg(16) Reference Counter - - HL HD - VD Range 0-4095 Pixels 0-1023 Pixels 0-1023 Pixels 0-4095 Pixels 0-2047 Lines 0-15 Lines Description 12-Bit Gray Code Counter Value 10-Bit HL-Counter Value HD Rise Position HD Last Line Length VD Counter Value VD Rise Position
SPECIAL NOTE ABOUT THE HDLEN REGISTER
The 12-bit HD counter value must be programmed using a gray code number. There is also a 4-clock cycle, set up period that must be considered when determining the HDLEN register value, as shown in Figure 22. As a result of the 4-clock cycle, setup period, the value of HDLEN is always equal to the actual number of pixels per line minus 4. For example, if there are 2100 pixels per line, HDLEN equals (2100 - 4) = 2096. The gray code value of 2096 is 0xC28, which is what would be programmed in the HDLEN register.
1
Register value must be a gray code number (see Gray Code Registers section).
VDLEN 11-BIT VD COUNTER 000 001 002 _ N < 2048
HDLEN 12-BIT GRAY COUNTER + SET- UP HLEN 10-BIT HL COUNTER
SET-UP
HDLASTLEN
VD
2
HD
1
04593-0-023
LINE LENGTH = HDLEN + 4
NOTES 1. THE SET-UP DELAY IS 4 CLI CYCLES. THE ACTUAL LENGTH OF ONE LINE IS 4 MORE CYCLES THAN VALUE SET IN HDLEN AND HDLASTLEN DUE TO SET-UP DELAY. 2. VDRISE REFERENCES THE 11-BIT VD-COUNTER. 3. HDRISE REFERENCES THE 10-BIT HL-CONTER. PROGRAMMABLE CLOCK POSITIONS 1. HDRISE (SYS_REG(16)) 2. VDRISE (SYS_REG(16))
Figure 22. VD and HD Horizontal Timing
Rev. A | Page 28 of 64
AD9929 HORIZONTAL CLAMPING AND BLANKING
The AD9929's horizontal clamping and blanking pulses are programmable to suit a variety of applications. As with the vertical timing generation, individual sequences are defined for each signal, which are then organized into multiple regions during image readout. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout, in order to accommodate different image transfer timing and high speed line shifts. The length of the last HD line is set using the HDLASTLEN register (Sys_Reg(1)). Figure 23 shows how no CLPOB pulse is asserted when the last HD length set by HDLASTLEN is shorter than the regular HD length set by HDLEN. Figure 24 shows how no CLPOB pulse is applied when the last HD length set by HDLASTLEN is longer than the regular HD length. Note that the CLPOB pulse is applied in the last line only when HDLASTLEN = HDLEN.
HD
CONTROLLING CLPOB CLAMP PULSE TIMING
The AFE horizontal CLPOB pulse is generated based on the 12-bit gray code counter. Once the length of the 12-bit gray code counter is set using the HDLEN register (Sys_Reg(12)), the CLPTOG1 and CLPTOG2 registers (Sys_Reg(15 and 16)) can be used to place the CLPOB pulse location, as shown in Figure 25. Table 19 lists all CLPOB registers that are used to configure and control the placement and output of the CLPOB pulse.
CLPOB LAST LINE
Figure 23. Last HD Shorter than Regular HD
HD
CLPOB
LAST LINE
Figure 24. Last HD Longer than Regular HD
Table 19. CLPOB Registers
Register Name CLPOB_CONT CLPOB_MODE Bit Width 1 1 Register Type Control (0x01) Control (0x01) Counter Reference - - Range Description CLPOB Control (0=CLPOB off, 1 =CLPOB On) CLPOB CCD Region Control (0 = Enable CLPENx Register Settings, 1 = Disable CLPENx Register Settings) CLPOB Toggle Position 1 (Gray Code Number) CLPOB Toggle Position 2 (Gray Code Number) CLPOB Control for CCD Region 0 (0 = CLPOB Disabled, 1 = CLPOB Enabled) CLPOB Control for CCD Region 1 (0 = CLPOB Disabled, 1 = CLPOB Enabled) CLPOB Control for CCD Region 2 (0 = CLPOB Disabled, 1 = CLPOB Enabled) CLPOB Control for CCD Region 3 (0 = CLPOB Disabled, 1 = CLPOB Enabled) CLPOB Control for CCD Region 4 (0 = CLPOB Disabled, 1 = CLPOB Enabled)
CLPTOG1 CLPTOG2 CLPEN0 CLPEN1 CLPEN2 CLPEN3 CLPEN4
12 12 1 1 1 1 1
Sys_Reg (15) Sys_Reg (15 and 16) Mode_Reg (2) Mode_Reg (2) Mode_Reg (2) Mode_Reg (2) Mode_Reg (2)
HD HD - - - - -
0 to 4095 pixel locations 0 to 4095 pixel locations
Rev. A | Page 29 of 64
04953-0-025
04593-0-024
AD9929
VD
HD
12-BIT GRAY COUNTER + SET-UP
CLPOB PROGRAMMABLE CLOCK POSITIONS 1. CLPTOG1 (SYS_REG (15)) 2. CLPTOG2 (SYS_REG (15 AND 16))
1
2
04593-0-026
Figure 25. Location of CLPOB using CLPTOG1 and CLPTOG2 Registers.
VD
HD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLPOB
CLPMASK (INTERNAL)
A 1 2 3 4 5
B
PROGRAMMING POSITIONS 1. SCP0 = 0 (FIXED), CLPEN0 = 1 2. SCP1 = 3, CLPEN1 = 0 3. SCP2 = 4, CLPEN2 = 1 4. SCP3 = 5, CLPEN3 = 0 5. SCP4 = 1, CLPEN4 = 1 NOTES 1. THE INTERNAL CLPMASK SIGNAL EXTENDS ONE EXTRA HD CYCLE FROM WHEN THE CLPMASK PERIOD CHANGES FROM LOW TO HIGH. AS A RESULT, ONE ADDITIONAL CLPOB PULSE IS MASKED AS SHOWN AT POSITIONS A AND B.
04593-0-027
Figure 26. CLPOB Outputs with CLPMODE = 0
CONTROLLING CLPOB CLAMP PULSE OUTPUTS
The registers in Table 19 are used for programming the CLPOB pulse. The CLPOB pulse is disabled in all CCD regions by setting CLPCNT = 0. The CLPTOGx (x = 0, 1) are used to set the CLPOB toggle positions. The CLPENx (x = 0, 1, 2, 3, and 4) are used to enable or disable the CLPOB pulse separately in each CCD region when CLPMODE = 0. The CLPEN registers have no effect if CLPMODE = 1. In this case, the CLPOB pulse is asserted in all CCD regions, regardless of the value set in the CLPENx registers. Figure 26 shows an example of the CLPOB pulse being disabled in CCD Regions 1 and 3 by setting CLPEN1 = 1 and CLPEN3 =1. Note that the CLPOB pulse remains disabled in the first line of the following CCD region.
Table 20. SCP and CLPEN
SCP[4:1]1 SCP0 SCP1 SCP2 SCP3 SCP4 CLPEN[4:0] CLPEN0 CLPEN1 CLPEN2 CLPEN3 CLPEN4
1
SCP0 is not a programmable register and therefore not listed in the register map tables. SCP0 is a fixed sequence and always starts at the falling edge of VD. Although this register is not programmable, the CLPEN0 register is still used to set whether the CLPOB pulse is enabled or disabled for this SCP0 region.
Rev. A | Page 30 of 64
AD9929
H1 AND H2 BLANKING
The AD9929 provides three options for controlling the period where H1 and H2 pulses get blanked. These options are normal H blanking, selective positioning for 2 H1 and H2 outputs, and extended blanking. In all cases, HBLKMASK is used to set the polarity of H1 during the blanking period. Table 21 describes the registers used to control H blanking.
Selective Positioning for Two H1 and H2 Outputs
For selective positioning operation, HPULSECNT = 1 and HBLKMASK = 0 or 1. In this mode, two H1 pulses are output during the blanking period. The location of these two pulse is set using the HBLKPOS register, as shown in Figure 28.
Extended Blanking
Extended blanking is enabled by setting HBLKEXT = 1. The HBLKEXT register uses the 9-bit BL counter to suspend operation of the HD and HL counters. This delays the blanking period by the length set in the BLLEN register, as shown in Figure 29.
Normal H-Blanking
For normal H-blanking operation, HPULSECNT = 0 and BLKMASK = 0 or 1. The HBLKPOS register isn't used in this mode. Figure 27 shows one example where HBLKMASK = 0 and H1 and H2 are blanked while HD is low. Table 21. H1 Blanking Registers
Register Name HBLKMASK HPULSECNT HBLKEXT H1BLKRETIME HBLKHPOS Bit Width 1 1 1 1 10 Control (0x03) Sys_Reg(11) Register Type Control (0x01) Control (0x0A) Control (0x0A) Description
Masking Polarity for H1 during Blanking Period1 (0 = Low, 1 = High) H Pulse Control during Blanking Period (0 = No Output during Blanking,1 = Output during Blanking ) H Pulse Blanking Extends Control2 (0 = Extended Blanking Disabled, 1 = Extended Blanking Enabled) Retimes the H1 HBLK to Internal Clock (0 = Retiming Disabled, 1 = Retiming Enabled) H1 Pulse ON Position during Blanking Period
1 2
H2 is always the opposite polarity of H1. The HBLKEXT extend control extends the blanking period by the number of counts set in the BLLEN register for the 9-bit BL counter.
HD HDRISE HBLK (INTERNAL) 1
H1
H2
RG
04593-0-028
NOTES 1. THE RISING EDGE OF HBLK IS ALWAYS THE SAME AS HDRISE
Figure 27. Normal H-Blanking Operation HBLKMASK = 0, HPULSECNT = 0, HBLKHPOS = XXX
Rev. A | Page 31 of 64
AD9929
HD
HBLK (INTERNAL)
H12 (INTERNAL)
RG
H1
NOTES 1. H2 IS THE OPPOSITE POLARITY OF H1
Figure 28. Selective H-Blanking Operation HBLKMASK = 0, HPULSECNT = 1, HBLKHPOS = 003.
BLLEN
9-BIT BL COUNTER VD
HD 1
H1 2
CLPOB
3
4
NOTES 1. POSITIONS 1, 2, 3 AND 4 ARE DELAYED BY THE VALUE OF BL COUNTER 2. VSG1, VSG2, V1-4 AND SUBCK PULSES ARE NOT DELAYED BY BL COUNTER
Figure 29. VD, HD, H1 and H2 Extended Blanking Operation HBLKEXT = 1.
Rev. A | Page 32 of 64
04593-0-030
04593-0-029
AD9929 VGATE MASKING OF XV1 TO XV4 AND CLPOB OUTPUTS
During slave mode operation, the SYNC/VGATE Pin 45 is configured as an input for an external VGATE signal. While operating in this mode, the external VGATE signal can be used to mask the XV1 to XV4 and CLPOB outputs. There are two options available for masking the XV1 to XV4 and CLPOB outputs. These options are determined by the setting of the MSHUT/VGATE_EN register located at Control Address 0x01. Examples of these two options are shown in Figure 30 and Figure 31. Figure 30 shows MSHUT/VGATE_EN = 0. In this example, the VGATE signal is internally latched on the falling
VD
edge of HD, resulting with the XV1 to XV4 and CLPOB outputs being masked when the internally latched VGATE signal is high. Figure 31 shows MSHUT/VGATE_EN = 1. In this example, the preprogrammed MSHUT signal blocks the VGATE input from masking XV1 to XV4 and CLPOB outputs while MSHUT is low. The internally latched VGATE signal only masks XV1 to XV4 and CLPOB when MSHUT is high, while operating in this mode.
HD
VGATE (PIN #45)
VGATE (INTERNAL)
XV1-XV4
XV1-XV4 AND CLPOB MASKED
XV1-XV4 AND CLPOB MASKED
Figure 30. Example of VGATE Input Masking V1 to V4 and CLPOB Outputs with MSHUT/VGATE_EN = 0
VD
HD
VGATE (PIN #45)
VGATE (INTERNAL)
MSHUT
XV1-XV4
XV1-XV4 AND CLPOB MASKED
Figure 31. Example of VGATE Input Masking V1to V4 and CLPOB Outputs with MSHUT/VGATE_EN = 1
Rev. A | Page 33 of 64
04590-0-032
CLPOB
04590-0-031
CLPOB
AD9929 VERTICAL TIMING GENERATION
The AD9929 provides a very flexible solution for generating vertical CCD timing and can support multiple CCDs and different system architectures. The 4-phase vertical transfer clocks XV1 to XV4 are used to shift each line of pixels into the horizontal output register of the CCD. The AD9929 vertical outputs can be individually programmed into four different vertical pulse patterns identified as VTP0, VTP1, VTP2, and VTP3. Each vertical pulse pattern is a unique set of preconfigured XV1 to XV4 sequences. Once the vertical patterns have been configured using the registers shown in Table 24, pointer registers are used to select in which region of the CCD a particular vertical pattern is output. The pointer registers are described in Table 22. Up to five unique CCD regions may be specified. Finally, the readout of the entire field is constructed by combining one or more of the individual regions sequentially. With up to five regions available, different steps of the readout such as high speed line shifts and vertical image transfer can be supported. Step 2: Create the individual vertical sequences (see Figure 33). Create the individual vertical sequences by assigning pulse repetitions to patterns VTP0, VTP1, VTP2, and VTP3 using the VTPREPx registers as shown in Table 25. The number of repetitions (VTPREPx) determines the number of pulse repetitions desired within a single line. Programming 1 for VTPREPx gives a single pulse, and setting to 0 provides a fixed dc output based on the start polarity value. Figure 33 shows an example of a VTPx sequence of two VTPx patterns by setting VTPREPx = 2. Step 3: Output Vertical Sequences into CCD Regions (see Figure 34). The AD9929 arranges individual sequences into CCD regions through the use of sequence pointers (VTPSEQPTRx) and vertical transfer pattern select (VTPSELx) registers, as described in Table 23. The VTPSEQPTRx registers are used to point to a desired VTPSELx register whose value determines what VTPx pattern is output on the XV1 to XV4 signals. For example, if VTPSEQPTR0 = 1 and VTPSEL1 = 2, the VTP2 pulse pattern would output while operating in Region 0 of the CCD. Step 4: Combining CCD Regions (see Figure 34). Build the entire field readout by combining multiple regions by using mode registers SCP0, SCP1, SCP2, SCP3, and SCP4. The individual CCD regions are combined into a complete field readout by using sequence change position (SCPx) pointers as described in Table 23. Figure 34 shows how each field is divided into multiple regions. This allows the user to change vertical timing during various stages of the image readout. The boundaries of each region are defined by the sequence change position (SCP). Each SCP is a 8-bit value representing the line number boundary region. A total of four SCPs allow up to five different region areas in the field to be defined. The first SCP0 is always hard-coded to line 0, and the remaining four SCPs are register programmable.
CREATING VERTICAL SEQUENCES
Figure 32 through Figure 34 provide an overview of how the vertical timing is generated in four basic steps. Step 1: Create the individual pulses for patterns VTP0, VTP1, VTP2, and VTP3 (see Figure 32). The registers shown in Table 22 are used to generate the individual vertical timing pulses, as shown in Figure 32. The VTPLENx determines the number of pixels between pulse repetitions. The start polarity (XVxSTARTPOLx) sets the starting polarity of the vertical sequence and can be programmed high or low. The first toggle position (XVxTOG1POSx) and second toggle position (XVxTOG2POSx) are the pixel locations within the line where the pulse transitions.
Rev. A | Page 34 of 64
AD9929
0
50
100
150
200
250
300
350
400
HD
XV1
1
2
3
XV2
4
5
6
XV3
7
8
9
XV4
10
11
VTPLENx [8:0] = 210
12
Figure 32. Step 1: Create Individual Vertical Pulses for VTP0, VTP1, VTP2, and VTP3 Patterns.
0 HD
50
100
150
200
250
300
350
400
XV1
1
2
3
XV2
4
5
6
XV3
7
8
9
XV4
10
11
12
04593-0-034
VTPLENx [8:0] = 210
Figure 33. Step 2: Create Individual Sequences for XV1 to XV4 Outputs by Assigning Pulse Repetitions to VTP0, VTP1, VTP2 and VTP3 Patterns. This Example Shows VTPREPx = 2
Rev. A | Page 35 of 64
04593-0-033
1. XV1STARTPOLx = 0 4. XV2STARTPOLx = 1 7. XV3STARTPOLx = 1 10. XV4STARTPOLx = 0
2. XV1TOG1x [8:0] = 50 5. XV2TOG1x [8:0] = 30 8. XV3TOG1x [8:0] = 110 11. XV4TOG1x [8:0] = 20
3. XV1TOG2x [8:0] = 130 6. XV2TOG2x [8:0] = 150 9. XV3TOG2x [8:0] = 180 12. XV4TOG2x [8:0] = 160
AD9929
CCD REGION 0 SCP0 (FIXED AT LINE 0)
VERTICAL TRANSFER PULSES SCP1 [7:0] CCD REGION 1
XV1 XV2 XV3 XV4
XV1 XV2 XV3 XV4
{ {
VTP0
XV1 XV2 XV3 XV4
VTP2
XV1 XV2 XV3 XV4
{ {
VTP1
SCP2 [7:0] CCD REGION 2
VTP3
SCP3 [7:0] CCD REGION 3
SCP4 [7:0] CCD REGION 4
SCP 0 REGION 0 (FIXED AT LINE 0) VD
SCP 1 REGION 1 (LINE #4)
SCP 2 REGION 2 (LINE #7)
SCP 4 REGION 4 (LINE # (N + 7))
HD
XV1
XV2
XV3
XV4
VTP0 VTPREP0 = 2
VTP0 VTPREP0 = 1
VTP2 VTPREP2 = 2
VTP1 VTPREP1 = 1
Figure 34. Steps 3 and 4: An Example of Building an Entire Field Readout by Assigning Sequences to Multiple CCD Regions
Rev. A | Page 36 of 64
04593-0-035
AD9929
Table 22. XV1 to XV4 Registers to Configure XXV1 to XXV4 Pulses for each VTP Pattern
Register Name VTPLEN0 XV1STARTPOL0 XV2STARTPOL0 XV3STARTPOL0 XV4STARTPOL0 XV1TOG1POS0 XV1TOG2POS0 XV2TOG1POS0 XV2TOG2POS0 XV3TOG1POS0 XV3TOG2POS0 XV4TOG1POS0 XV4TOG2POS0 VTPLEN1 XV1STARTPOL1 XV2STARTPOL1 XV3STARTPOL1 XV4STARTPOL1 XV1TOG1POS1 XV1TOG2POS1 XV2TOG1POS1 XV2TOG2POS1 XV3TOG1POS1 XV3TOG2POS1 XV4TOG1POS1 XV4TOG2POS1 VTPLEN2 XV1STARTPOL2 XV2STARTPOL2 XV3STARTPOL2 XV4STARTPOL2 XV1TOG1POS2 XV1TOG1POS2 XV1TOG2POS2 XV2TOG1POS2 XV3TOG1POS2 XV3TOG2POS2 XV4TOG1POS2 XV4TOG2POS2 Bit Width 9 1 1 1 1 9 9 9 9 9 9 9 9 9 1 1 1 1 9 9 9 9 9 9 9 9 9 1 1 1 1 9 9 9 9 9 9 9 9 Register Type Sys_Reg(1) Sys_Reg(1) Sys_Reg(1) Sys_Reg(1) Sys_Reg(1) Sys_Reg(1) Sys_Reg(1) Sys_Reg(1 & 2) Sys_Reg(2) Sys_Reg(2) Sys_Reg(2 & 3) Sys_Reg(3) Sys_Reg(3) Sys_Reg(3) Sys_Reg(3) Sys_Reg(3) Sys_Reg(4) Sys_Reg(4) Sys_Reg(4) Sys_Reg(4) Sys_Reg(4 Sys_Reg(4 & 5) Sys_Reg(5) Sys_Reg(5) Sys_Reg(5 & 6) Sys_Reg(6) Sys_Reg(6) Sys_Reg(6) Sys_Reg(6) Sys_Reg(6) Sys_Reg(6) Sys_Reg(6) Sys_Reg(7) Sys_Reg(7) Sys_Reg(7) Sys_Reg(7 & 8) Sys_Reg(8) Sys_Reg(8) Sys_Reg(8) V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter Reference Counter V Counter Range 0-511 High/Low High/Low High/Low High/Low 0-511 0-511 0-511 0-511 0-511 0-511 0-511 0-511 0-512 High/Low High/Low High/Low High/Low 0-511 0-511 0-511 0-511 0-511 0-511 0-511 0-511 0-512 High/Low High/Low High/Low High/Low 0-511 0-511 0-511 0-511 0-511 0-511 0-511 0-511 Description Length between Repetitions XV1 Starting Polarity for VTP0 (0 = Low, 1 = High) XV2 Starting Polarity for VTP0 (0 = Low, 1 = High) XV3 Starting Polarity for VTP0 (0 = Low, 1 = High) XV4 Starting Polarity for VTP0 (0 = Low, 1 = High) XV1 Toggle Position 1 for VTP0 XV1 Toggle Position 2 for VTP0 XV2 Toggle Position 1 for VTP0 XV2 Toggle Position 2 for VTP0 XV3 Toggle Position 1 for VTP0 XV3 Toggle Position 2 for VTP0 XV3 Toggle Position 1 for VTP0 XV3 Toggle Position 2 for VTP0 Length between Repetitions XV1 Starting Polarity for VTP1 (0 = Low, 1 = High) XV2 Starting Polarity for VTP1 (0 = Low, 1 = High) XV3 Starting Polarity for VTP1 (0 = Low, 1 = High) XV4 Starting Polarity for VTP1 (0 = Low, 1 = High) XV1 Toggle Position 1 for VTP1 XV1 Toggle Position 2 for VTP1 XV2 Toggle Position 1 for VTP1 XV2 Toggle Position 2 for VTP1 XV3 Toggle Position 1 for VTP1 XV3 Toggle Position 2 for VTP1 XV3 Toggle Position 1 for VTP1 XV3 Toggle Position 2 for VTP1 Length between Repetitions XV1 Starting Polarity for VTP2 (0 = Low, 1 = High) XV2 Starting Polarity for VTP2 (0 = Low, 1 = High) XV3 Starting Polarity for VTP2 (0 = Low, 1 = High) XV4 Starting Polarity for VTP2 (0 = Low, 1 = High) XV1 Toggle Position 1 for VTP2 XV1 Toggle Position 1 for VTP2 XV1 Toggle Position 2 for VTP2 XV2 Toggle Position 1 for VTP2 XV3 Toggle Position 1 for VTP2 XV3 Toggle Position 2 for VTP2 XV3 Toggle Position 1 for VTP2 XV3 Toggle Position 2 for VTP2 VTP Pattern
VTP0
VTP1
VTP2
Rev. A | Page 37 of 64
AD9929
Register Name VTPLEN3 XV1STARTPOL3 XV2STARTPOL3 XV3STARTPOL3 XV4STARTPOL3 XV1TOG1POS3 XV1TOG2POS3 XV2TOG1POS3 XV2TOG2POS3 XV3TOG1POS3 XV3TOG2POS3 XV4TOG1POS3 XV4TOG2POS3 Bit Width 9 1 1 1 1 9 9 9 9 9 9 9 9 Register Type Sys_Reg(9) Sys_Reg(9) Sys_Reg(9) Sys_Reg(9) Sys_Reg(9) Sys_Reg(9) Sys_Reg(9) Sys_Reg(9 &10) Sys_Reg(10) Sys_Reg(10) Sys_Reg(10&11) Sys_Reg(11) Sys_Reg(11) V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter Reference Counter V Counter Range Description 0-512 High/Low High/Low High/Low High/Low 0-511 0-511 0-511 0-511 0-511 0-511 0-511 0-511 Length between Repetitions XV1 Starting Polarity for VTP3 (0 = Low, 1 = High) XV1 Starting Polarity for VTP3 (0 = Low, 1 = High) XV1 Starting Polarity for VTP3 (0 = Low, 1 = High) XV1 Starting Polarity for VTP3 (0 = Low, 1 = High) XV1 Toggle Position 1 for VTP3 XV1 Toggle Position 2 for VTP3 XV2 Toggle Position 1 for VTP3 XV2 Toggle Position 2 for VTP3 XV3 Toggle Position 1 for VTP3 XV3 Toggle Position 2 for VTP3 XV3 Toggle Position 1 for VTP3 XV3 Toggle Position 2 for VTP3 VTP Pattern
VTP3
Table 23. Mode_A and Mode_B Registers for VTPx Selection
Register Name VTPSEQPTR01 Bit Width 3 Register Type Mode_Reg(2) Range Description Vertical Transfer Pulse Pointer used in CCD Region 0 (0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3, 4 = VTPSEL0 for Even Line and VTPSEL1 for Odd Line, 5 = VTPSEL2 for Even Line and VTPSEL3 for Odd Line) Vertical Transfer Pulse Pointer used in CCD Region 1 (0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3, 4 = VTPSEL0 for Even Line and VTPSEL1 for Odd Line, 5 = VTPSEL2 for Even Line and VTPSEL3 for Odd Line) Vertical Transfer Pulse Pointer used in CCD Region 2 (0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3, 4 = VTPSEL0 for Even Line and VTPSEL1 for Odd Line, 5 = VTPSEL2 for Even Line and VTPSEL3 for Odd Line) Vertical Transfer Pulse Pointer used in CCD Region 3 (0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3, 4 = VTPSEL0 for Even Line and VTPSEL1 for Odd Line, 5 = VTPSEL2 for Even Line and VTPSEL3 for Odd Line) Vertical Transfer Pulse Pointer used in CCD Region 4 (0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3, 4 = VTPSEL0 for Even Line and VTPSEL1 for Odd Line, 5 = VTPSEL2 for Even Line and VTPSEL3 for Odd Line) 0 = VTP0, 1 = VTP1, 2 = VTP2, 3 = VTP3 0 = VTP0, 1 = VTP1, 2 = VTP2, 3 = VTP3 0 = VTP0, 1 = VTP1, 2 = VTP2, 3 = VTP3 0 = VTP0, 1 = VTP1, 2 = VTP2, 3 = VTP3 Number of VTP0 Pulse Repetitions within a Line Number of VTP1 Pulse Repetitions within a Line Number of VTP2 Pulse Repetitions within a Line Number of VTP3 Pulse Repetitions within a Line
VTPSEQPTR11
3
Mode_Reg(2)
VTPSEQPTR21
3
Mode_Reg(2)
VTPSEQPTR31
3
Mode_Reg(2)
VTPSEQPTR41 VTPSEL0 VTPSEL1 VTPSEL2 VTPSEL3 VTPREP0 VTPREP1 VTPREP2 VTPREP3
3 2 2 2 2 3 3 3 3
Mode_Reg(2) Mode_Reg(3) Mode_Reg(3) Mode_Reg(3) Mode_Reg(3) Mode_Reg(3) Mode_Reg(4) Mode_Reg(4) Mode_Reg(4)
0-7 0-7 0-7 0-7
1
Register settings 6 and 7 are not used.
Table 24. Mode_A and Mode_B Registers for CCD Region Selection
Register Name SCP1 SCP2 SCP3 SCP4 Bit Width 8 8 8 8 Register Type Mode_Reg(2) Mode_Reg(2) Mode_Reg(2) Mode_Reg(2) Range 0-255 lines 0-255 lines 0-255 lines 0-255 lines
Rev. A | Page 38 of 64
Description Sequence Change Position 1 Sequence Change Position 2 Sequence Change Position 3 Sequence Change Position 4
AD9929
SPECIAL VERTICAL SWEEP MODE OPERATION
The AD9929 contains a special mode of vertical timing operation called sweep mode. This mode is used to generate a continuous number of repetitive vertical pulses that span multiple HD lines. One example of where this mode may be needed is at the start of the CCD readout operation. At the end of the image exposure, but before the image is transferred by the sensor gate pulses, the vertical interline CCD registers should be clean of all charge. This can be accomplished by quickly shifting out any charge with a long series of pulses on the V1 to V4 outputs. This operation spans multiple HD line lengths. Normally the sequences are contained within one HD line length but with the sweep mode enabled, the HD boundaries will be ignored until the region is finished. The special vertical sweep mode operation is only output in CCD Region 0 and CCD Region 3 (see Figure 34), as shown in Figure 37 and Figure 38. The SVREP_MODE register located at
HD
Control Address 0x0A is used to enable and configure the special sweep mode operation, as described in Table 25. The maximum number of repeats in each region is 2048 while operating in this mode using the SVREP0 and SVREP3 Mode_Reg(4) registers. Table 25. Description of SVREP_MODE Register
SVREP_MODE 0 0 1 1 Description of Sweep Mode Operation 0 Normal Vertical Timing Operation in all CCD Regions 1 Special Vertical Sweep Mode Timing Output in CCD Region 0 Only 0 Special Vertical Sweep Mode Timing Output in CCD Region 3 Only 1 Special Vertical Sweep Mode Timing Output in CCD Region0 and CCD Region 3
XV1-XV4
Figure 35. Nonoverlapping Example while Operating in Normal Vertical Timing Operation SVREP_MODE = 0 and VTPREPx = 4
HD NOT OUTPUT BECAUSE THE 8TH REPETITION OVERLAPS WITH HD XV1-XV4
Figure 36. Overlapping Example while Operating in Normal Vertical Timing Operation SVREP_MODE = 0 and VTPREPx = 8
SCP0 CCD REGION 0 HD 0 1 2 0
04593-0-038
SCP1 = 3
XV1-XV4
Figure 37. Sweep Mode Timing Example with SVREP_MODE = 1 and SVREP0 = 28
SCP3 CCD REGION 3 HD 0 1 2 0 SCP4 = 3
XV1-XV4
Figure 38. Sweep Mode Timing Example with SVREP_MODE = 2 and SVREP3 = 28
Rev. A | Page 39 of 64
04593-0-039
04593-0-037
04593-0-036
AD9929
SPECIAL VERTICAL TIMING (SPATS)
The AD9929 provides additional special vertical timing generation (SPATs), which is applied in the same line as the VSG pulse. The SPAT timing allows for an additional vertical output pulse in the VSG line. The additional vertical output pulse can be applied to either XV1, XV2, XV3 or XV4, according to the value of the SPATLOGIC register. Table 26 lists the registers used to generate the SPATs, and Table 27 describes the SPATLOGIC settings and operation. Figure 39 and Figure 40 show AND and OR SPAT pulse examples using four SPAT toggle positions. As shown in these figures, the internal SPAT timing for the AND case initially starts high and then goes low at the first XVxSPAT_TOG1 position. In the OR case, the internal SPAT timing initially starts low and then toggles high at the first XVxSPAT_TOG1 position. This provides the ability to output the second vertical pulse when the internal XVx pulse is in both high and low states. Note that although Figure 39 and Figure 40 show four SPAT toggle positions, two SPAT toggle positions can be applied by setting XVxSPAT_TOG3 = XVxSPAT_TOG4 = 0x1FFF.
Table 26. HD and VD Registers
Register Name SPAT_EN SPATLOGIC XV1SPAT_TOG1 XV1SPAT_TOG2 XV1SPAT_TOG3 XV1SPAT_TOG4 XV2SPAT_TOG1 XV2SPAT_TOG2 XV2SPAT_TOG3 XV2SPAT_TOG4 XV3SPAT_TOG1 XV3SPAT_TOG2 XV3SPAT_TOG3 XV3SPAT_TOG4 XV4SPAT_TOG1 XV4SPAT_TOG2 XV4SPAT_TOG3 XV4SPAT_TOG4 XV1SPAT_TOG1 XV1SPAT_TOG2 XV1SPAT_TOG3 XV1SPAT_TOG4 Bit Width 1 4 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 Register Type Control (Address 0x01) Control (Address 0x0A) Control (Address 0x17) Control (Address 0x18) Mode_A_Reg(5) Mode_A_Reg(5) Control (Address 0x19) Control (Address 0x1A) Mode_A_Reg(5) Mode_A_Reg(5) Control (Address 0x1B) Control (Address 0x1C) Mode_A_Reg(5) Mode_A_Reg(5) Control (Address 0x1D) Control (Address 0x1E) Mode_A_Reg(5) Mode_A_Reg(5) Control (Address 0x1F) Control (Address 0x20) Mode_B_Reg(5) Mode_B_Reg(5) Reference Counter - - ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192
Rev. A | Page 40 of 64
Range (Pixels)
Description SPAT Enable Control (0 = SPAT Disabled, 1 = SPAT Enabled) SPAT Logic Setting XV1SPAT Toggle Position #1 (Mode_A Active) XV1SPAT Toggle Position #2 (Mode_A Active) XV1SPAT Toggle Position #3 (Mode_A Active) XV1SPAT Toggle Position #4 (Mode_A Active) XV2SPAT Toggle Position #1 (Mode_A Active) XV2SPAT Toggle Position #2 (Mode_A Active) XV2SPAT Toggle Position #3 (Mode_A Active) XV2SPAT Toggle Position #4 (Mode_A Active) XV3SPAT Toggle Position #1 (Mode_A Active) XV3SPAT Toggle Position #2 (Mode_A Active) XV3SPAT Toggle Position #3 (Mode_A Active) XV3SPAT Toggle Position #4 (Mode_A Active) XV4SPAT Toggle Position #1 (Mode_A Active) XV4SPAT Toggle Position #2 (Mode_A Active) XV4SPAT Toggle Position #3 (Mode_A Active) XV4SPAT Toggle Position #4 (Mode_A Active) XV1SPAT Toggle Position #1 (Mode_B Active) XV1SPAT Toggle Position #2 (Mode_B Active) XV1SPAT Toggle Position #3 (Mode_B Active) XV1SPAT Toggle Position #4 (Mode_B Active)
AD9929
Register Name XV2SPAT_TOG1 XV2SPAT_TOG2 XV2SPAT_TOG3 XV2SPAT_TOG4 XV3SPAT_TOG1 XV3SPAT_TOG2 XV3SPAT_TOG3 XV3SPAT_TOG4 XV4SPAT_TOG1 XV4SPAT_TOG2 XV4SPAT_TOG3 XV4SPAT_TOG4 Bit Width 13 13 13 13 13 13 13 13 13 13 13 13 Register Type Control (Address 0x21) Control (Address 0x22) Mode_B_Reg(5) Mode_B_Reg(5) Control (Address 0x23) Control (Address 0x24) Mode_B_Reg(5) Mode_B_Reg(5) Control (Address 0x25) Control (Address 0x26) Mode_B_Reg(5) Mode_B_Reg(5) Reference Counter ST ST ST ST ST ST ST ST ST ST ST ST Range (Pixels) 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 Description XV2SPAT Toggle Position #1 (Mode_B Active) XV2SPAT Toggle Position #2 (Mode_B Active) XV2SPAT Toggle Position #3 (Mode_B Active) XV2SPAT Toggle Position #4 (Mode_B Active) XV3SPAT Toggle Position #1 (Mode_B Active) XV3SPAT Toggle Position #2 (Mode_B Active) XV3SPAT Toggle Position #3 (Mode_B Active) XV3SPAT Toggle Position #4 (Mode_B Active) XV4SPAT Toggle Position #1 (Mode_B Active) XV4SPAT Toggle Position #2 (Mode_B Active) XV4SPAT Toggle Position #3 (Mode_B Active) XV4SPAT Toggle Position #4 (Mode_B Active)
Table 27. SPATLOCIC Register (Address 0x0A)
SPATLOGIC[3:0] 3 2 XV4 XV3 SPAT Description 1 XV2 0 XV1 0 = OR, 1 = AND
Rev. A | Page 41 of 64
AD9929
500 540 600 640 VD
HD
13-BIT ST COUNTER (FIXED)
INTERNAL XV2 WITHOUT SPAT APPLIED
INTERNAL SPAT TIMING FOR XV2 WITH SPATLOGIC = 1
1
2
3
4
XV2 OUTPUT WITH SPAT APPLIED
XVSGx VSG LINE NOTES 1. THE XVxSPAT_TOG1 AND XVxSPAT_TOG2 REGISTERS REFERENCE THE 13-BIT ST COUNTER. 2. THE INTERNAL SPAT TIMING IS APPLIED IN THE SAME LINE AS THE XVSGx PULSE. PROGRAMMABLE CLOCK POSITIONS 1. XVXSPAT_TOG1 (PROGRAMMABLE AT CONTROL REGS) 3. XVXSPAT_TOG3 (PROGRAMMABLE AT MODE_REGS) 2. XVXSPAT_TOG2 (PROGRAMMABLE AT CONTROL REGS) 4. XVXSPAT_TOG4 (PROGRAMMABLE AT MODE_REGS)
04593-0-040
Figure 39. SPAT Example for XV2 with XV2SPAT_TOG1 = 500, XV2SPAT_TOG2 = 540, XV2SPAT_TOG3 = 600, XV2SPAT_TOG4 = 640, and SPATLOGIC = XX1X
500 540 600 640
VD
HD
13-BIT ST COUNTER (FIXED)
INTERNAL XV1 WITHOUT SPAT APPLIED
INTERNAL SPAT TIMING FOR XV1 WITH SPATLOGIC = 0
1
2
3
4
XV1 OUTPUT WITH SPAT APPLIED
XVSGx VSG LINE
04593-0-041
NOTES 1. THE XVxSPAT_TOG1 AND XVxSPAT_TOG2 REGISTERS REFERENCE THE 13-BIT ST COUNTER. 2. THE INTERNAL SPAT TIMING IS APPLIED IN THE SAME LINE AS THE XVSGx PULSE. PROGRAMMABLE CLOCK POSITIONS 1. XVXSPAT_TOG1 (PROGRAMMABLE AT CONTROL REGS) 3. XVXSPAT_TOG3 (PROGRAMMABLE AT MODE_REGS) 2. XVXSPAT_TOG2 (PROGRAMMABLE AT CONTROL REGS) 4. XVXSPAT_TOG4 (PROGRAMMABLE AT MODE_REGS)
Figure 40. SPAT (OR) Example for XV1 with XV1SPAT_TOG1 = 500, XV1SPAT_TOG2 = 540, XV1SPAT_TOG3 = 600, XV1SPAT_TOG4 = 640, and SPATLOGIC = XXX0
Rev. A | Page 42 of 64
AD9929 V1 TO V4 AND SUBCK OUTPUT POLARITIES
As shown in Figure 41, the XV1 to XV4 and XSUBCK are output signals from the AD9929 timing generator, whereas the V1 to V1 and SUBCK are output signals from the AD9929 vertical driver. The V1 to V4 and SUBCK polarities are not the same as the internal XV1 to XV4 and XSUBCK polarities configured by the AD9929 registers. Table 28 through Table 32 describe the output polarities for these signals versus their input levels. These tables must be referred to when determining the register settings for the desired output levels. Figure 46 shows an example of the V3 output. Table 28. V1 Output Polarity
XV1 L L H H V-Driver Input XVSG1 L H L H V1 Output VH1 VM1 VL VL
V-DRIVER XV1 XVSG1 XV2 TIMING GENERATOR XV3 XVSG2 XV4 XSUBCK V2 V3 V4 SUBCK V1
Figure 41. Internal XV1 to XV4 and XSUBCK Signals
Table 31. V3 Output Polarity
V-Driver Input XV3 L L H H V3 Output XVSG2 L H L H VH1 VM1 VL VL
Table 29. V2 Output Polarity
V-Driver Input XV2 L H V2 Output VM2 VL
Table 32. V4 Output Polarity Table 30. SUBCK Output Polarity
V-Driver Input XSUBCK L H SUBCK Output VH2 VL V-Driver Input XV4 L H V4 Output VM2 VL
XV1 XV3 50% 50%
XVSG1 XVSG3 50% 50%
tPLM1
tPMH
90%
tPHM
90%
tPML1
VH1
10% 90% V1 V3 10%
10%
tR2
tF1
90% 10%
VM1
VL
tR1
tF2
Figure 42. V1 and V3 Transmission Delays and Rise Times
Rev. A | Page 43 of 64
04593-0-043
04593-0-042
V-DRIVER LOGIC
V-DRIVER BUFFERS
AD9929
50% XV2 XV4 50%
tPML2
V2 V4 90% 10%
tPLM2
VM2 90%
04593-0-044
04593-0-045
10%
VL
tF3
tR3
Figure 43. V2 and V4 Transmission Delays and Rise Times
XSUBCK 50% 50%
tPLH
90% 10%
tPHL
90% 10% VH2
SUBCK
VL
tR4
tF4
Figure 44. SUBCK Transmission Delays and Rise Times
XV1
XVSG1
VH1 VM1 VL
04593-0-046
V1
Figure 45. Example Showing V1 Output versus XV1 and XVSG1 Signals
XV3
XVSG2
VH1 VM1 VL
04593-0-047
V3
Figure 46. Example Showing V3 Output versus XV3 and XVSG2 Signals
Rev. A | Page 44 of 64
AD9929
XV2 XV4
VM2 V2 V4 VL
Figure 47. Example Showing V2 and V4 Outputs versus XV2 and XV4 Signals
XSUBCK
04593-0-048
VH2 SUBCK VL
Figure 48. Example Showing SUBCK Output versus XSUBCK Signal
Rev. A | Page 45 of 64
04593-0-049
AD9929 TIMING CONTROL
ELECTRONIC SHUTTER TIMING CONTROL
CCD image exposure time is controlled through the use of the CCD substrate clock signal (XSUBCK), which pulses the CCD substrate to clear out accumulated charges prior to the exposure period. The AD9929 supports three types of electronic shuttering: normal shutter mode, suppression shutter mode, and high speed shutter mode. Table 34 contains the registers required for programming of XSUBCK pulses for each mode.
Single Pulse Mode
In addition to the normal operating XSUBCK pulse, one additional XSUBCK pulse can be applied within the HD line while operating in this mode. As shown in Figure 49, the location of the additional XSUBCK pulse is adjustable by setting the XSUBCK_HPNUM register as described in Table 33. Finer resolution of the exposure time is possible using this mode by adding an additional XSUBCK pulse in the line, as shown in Figure 54.
Normal Shutter Mode
Figure 49 shows the VD and XSUBCK output for normal shutter mode. The XSUBCK pulses once per line. The number of XSUBCK pulses per field can be programmed by setting register XSUBCKNUM (Address 0x0B). As shown in Figure 49, the XSUBCK pulses always begin on the line after the sensor gate, as specified by XVSGACTLINE (Mode_Reg(1)).
Multiple Pulse Mode
In addition to the normal operating XSUBCK pulse, up to seven sequential XSUBCK pulses can be applied within the same line while operating in this mode. As shown in Figure 54, the number of additional XSUBCK pulses is selectable by setting XSUBCKMODE_HP = 1, and the XSUBCK_HPNUM registers as described in Table 33. Table 33. Single and Multiple Pulse Mode
XSUBCKNUM_HP 0 Single Pulse Mode Normal Shutter Mode Operation Position #1 Position #2 Position #3 Position #4 Position #5 Position #6 Position #7 XSUBCKMODE_HP 1 Multiple Pulse Mode Normal Shutter Mode Operation 1 additional pulse 2 additional pulses 3 additional pulses 4 additional pulses 5 additional pulses 6 additional pulses 7 additional pulses
SUBCK Suppression Mode
Normally, the XSUBCKs begin to pulse on the line following the last sensor gate line (VSG). With some CCDs, the first XSUBCK following the VSG line needs to be suppressed. The XSUBCKSUPPRESS register allows for this suppression. The first XSUBCK following the last VSG pulse is suppressed when XSUBCKSUPPRESS = 1, as shown in Figure 50.
High Precision Shutter Mode
The high speed shutter mode can be operated in two different modes, known as single pulse mode and multiple pulse mode. These modes are set up by programming the XSUBCKNUM_HP register and XSUBCKMODE_HP register, as described in Table 28, Table 33, and shown in Figure 52 and Figure 54.
0 1 2 3 4 5 6 7
Table 34. XSUBCK Registers
Register Name XSUBCKNUM XSUBCKSUPPRESS XSUBCK_EN XSUBCKMODE_HP XSUBCKNUM_HP XSUBCK1TOG1 XSUBCK1TOG2 XSUBCK2TOG1 XSUBCK2TOG2 XSUBCKSEL Bit Width 11 1 1 1 3 9 9 9 9 1 Register Type Control (Address 0x0B) Control (Address 0x01) Control (Address 0x0B) Control (Address 0x01) Control (Address 0x0B) System_Reg(14) System_Reg(14) System_Reg(15) System_Reg(15) Mode_Reg(2) Reference Counter - - - - - OL Counter OL Counter OL Counter OL Counter - Range 0-2047 Number of Pulses 0-1 Number of Pulses - - 0-7 Number of Pulses 0-511 Pixel Location 0-511 Pixel Location 0-511 Pixel Location 0-511 Pixel Location - Description Number of XSUBCK Pulses per Field. Suppress First XSUBCK after Last XVSG Line Pulse XSUBCK Output Enable Control (0 = Disable, 1 = Enable) High Speed Shutter Mode Operation High Speed Shutter XSUBCLK Position/Number XSUBCLK1 1st Toggle Position XSUBCLK1 2nd Toggle Position XSUBCLK2 1st Toggle Position XSUBCLK2 2nd Toggle Position (0 = XSUBCK1, 1 = XSUBCK2)
Rev. A | Page 46 of 64
AD9929
VD
HD
XVSG1XVSG2
tEXP
1 2 3
tEXP
XSUBCK
NUMBER OF XSUBCK PULSES WITHIN THE FIELD IS SET BY USING THE XSUBCKNUM REGISTER. IN THIS EXAMPLE, XSUBCKNUM = 2.
Figure 49. Normal Shutter Mode
VD
HD
XVSG1XVSG2
tEXP
XSUBCK 1 XSUBCK PROGRAMMABLE SETTINGS 1. SETTING XSUBCKSUPPRESS REGISTER = 1 SUPRESSES THIS FIRST XSUBCK FOLLOWING XVSG PULSE.
tEXP
Figure 50. XSUBCK Suppression Mode
HD OLEN 9-BIT 0L-COUNTER
XSUBCK
1 NORMAL SHUTTER MODE PULSE ALWAYS OUTPUT
2
3
4
5
6
7
04593-0-052
Figure 51. Electronic Shutter Timing
HD
9-BIT OL-COUNTER
XSUBCK
04593-0-053
1
Figure 52. Electronic Shutter Timing Example with XSUBCKMODE_HP = 0 and XSUBCKNUM_HP = 1
Rev. A | Page 47 of 64
04593-0-051
04593-0-050
SUBCK PROGRAMMABLE SETTINGS 1. XSUBCK STARTING POLARITY IS ALWAYS HIGH. 2. FALLING EDGE OF XSUBCK IS SET USING THE XSUBCK1TOG1 OR XSUBCK2TOG1 REGISTERS. 3. RISING EDGE OF XSUBCK IS SET USING THE XSUBCK1TOG2 OR XSUBCK2TOG2 REGISTERS.
AD9929
VSG TIMING
The VSG Timing is controlled using the registers in Table 35. Two unique preprogrammed VSG pulses can be configured using the XVSGTOG_x (x = 0, 1) registers. As shown in Figure 55, the period of the VSG pulse is set by programming the XVSGLEN_x registers. The XVSGSELx (x = 1, 2) can then be used to select the XVSGTOG_0 or XVSGTOG_1 pulse. Figure 55 also shows an example of the XVSG pulse being output in the fourth line by setting the XVSGACTLINE = 3. The XVSG pulses references the 13-bit fixed ST counter, which starts counting from the line set in the XVSGACTLINE register. The 13-bit counter allows for overlapping of the XVSG pulse into the next line if needed. Figure 53 describes the XVSG1 and XVSG2 MUX operation using the XVSGSELx registers.
XVSGTOG_0 XVSGTOG_1 XVSG1 (APPLIED TO XV1)
XVSGSEL1
XVSGTOG_0 XVSGTOG_1 XVSG2 (APPLIED TO XV3)
04593-0-055
XVSGSEL2
Figure 53. XVSGSELx Registers
HD
9-BIT OL-COUNTER XSUBCK
04593-0-054
1
2
3
Figure 54. Electronic Shutter Timing Example with XSUBCKMODE_HP = 1 and XSUBCKNUM_HP = 3.
Table 35. VSG Registers
Register Name XVSGMASK Bit Width 6 Register Type Control (Address 0x0A) Reference Counter - Range - Description VSG Mask Control (00 = XVSG1 Masked, XVSG2 Masked) (02 = XVSG1 Not Masked, XVSG2 Masked) (08 = XVSG1 Masked, XVSG2 Not Masked) (0A= XVSG1 Not Masked, XVSG2 Not Masked) XVSG Output Enable Control (0 = Disable XVSG Outputs, 1 = Enable XVSG Outputs) XVSGTOG_0 Toggle Position XVSG TOG_1 Toggle Position XVSGTOG_0 Pulse Width XVSGTOG_1 Pulse Width XVSG1 Selector (0 = XVSGTOG_0 Applied on XVSG1, 1 = XVSGTOG_1 Applied on XVSG1) XVSG2 Selector (0 = XVSGTOG_0 Applied on XVSG2, 1 = XVSGTOG_1 Applied on XVSG2 ) VSG Active Line
XVSG_EN XVSGTOG_0 XVSGTOG_1 XVSGLEN_0 XVSGLEN_1 XVSGSEL1
1 11 11 8 8 1
Control (Address 0x0B) Sys_Reg(13) Sys_Reg(13) Sys_Reg(14) Control (Address 0x0F) Mode_Reg(1)
- ST ST ST ST -
High/Low 0-8191 Pixels 0-8191 Pixels 0-255 Pixels 0-255 Pixels High/Low
High/Low XVSGSEL2 XVSGACTLINE 1 7 Mode_Reg(1) Mode_Reg(1) - 0-128 Lines
Rev. A | Page 48 of 64
AD9929
VD
HD 0 13-BIT ST COUNTER (FIXED) XVSGACTLINE XVSGTOG_0 1 XVSGLEN_0 1 2 3
XVSGLEN_1 XVSGTOG_1
04593-0-056
2
NOTES 1. XVSGTOG_x (x = 0, 1) REFERENCES THE 13-BIT ST COUNTER 2. XVSGACTLINE (PROGRAMMABLE AT MODE_REG(1)) 3. XVSGLEN (PROGRAMMABLE AT SYS_REG(14)) PROGRAMMABLE CLOCK POSITIONS 1. XVSGTOG_0 (PROGRAMMABLE AT SYS_REG(13)) 2. XVSGTOG_1 (PROGRAMMABLE AT SYS_REG(13))
Figure 55. Example of VSG Pulse
1 SERIAL WRITES 4
2
VD
5
HD
3
VSUB
6
04593-0-058
2 LINES
3 LINES
Figure 56. VSUB Timing Example
VSUB TIMING
The CCD readout bias (VSUB) can be programmed to accommodate different CCDs. VSUB on and off toggle positions and polarity are controlled using VSUBTOG (Address 0x0D) and VSUBPOL (Address 0x0D) registers, respectively, as described in Table 36. Since the VSUBTOG is an 11-bit register, the VSUB on position is programmable within any line. Figure 56 shows an example of controlling VSUB using these registers. Table 36. VSUB Registers
Register Name VSUBPOL VSUBTOG Bit Width 1 11 Register Type Control Control Range (Lines) - 0-2048
VSUB Placement and Polarity
Figure 56 shows the sequence of events for programming the VSUB on and off toggle positions and polarity. 1. 2. Program VSUBTOG = 2 and VSUBPOL = 1. Since the VSUBTOG and VSUBPOL are VD synchronous type registers, the falling edge of VD updates the serial writes from Step 1. VSUB is asserted high after two HD cycles. Program VSUBTOG = 3 and VSUBPOL = 0. Since the VSUBTOG and VSUBPOL are VD synchronous type registers, the falling edge of VD updates the serial writes from Step 4. VSUB is asserted low after three HD cycles.
3.
Description (0 = Low, 1 = High) VSUB toggle position
4. 5.
6.
Rev. A | Page 49 of 64
AD9929
MSHUT TIMING
MSHUT Basic Operation
The AD9929 provides an MSHUT output pulse that can be configured to control the mechanical shutter of the camera. The registers used to control the MSHUT pulse are listed in Table 37. The MSHUT pulse can be placed at the start of any line by using the 11-bit MSHUTPOS register. The MSHUT pulse width Table 37. MSHUT and STROBE Registers
Register Name MSHUTPAT MSHUTINIT MSHUTEN MSHUTPOS MSHUTPOS_HP MSHUTLEN STROBE_EN Bit Width 2 1 1 11 3 8 1 Register Type Control (Address 0x01) Control (Address 0x0C) Control (Address 0x0C) Control (Address 0x0C) Control (Address 0x0C) Sys_Reg(13) Control (Address 0x0B) Description Selects MSHUT Pattern. (0 = MSHUTPAT0, 1 = MSHUTPAT1, 2 = MSHUTPAT2, 3 = MSHUTPAT3) MSHUT Initialize (1 = MSHUT Output Held Low, 0 = Normal Operation Resumes) MSHUT Control (0 = MSHUT Held at Last State, 1 = MSHUT Output Enabled for Normal Operation) MSHUT Position during Normal Operation MSHUT Position during High Precision Operation MSHUT Pattern Length. STROBE Output Enable Control (0 = STROBE Output Held Low, 1 = Enable STROBE Output)
is controlled by using the MSHUTLEN register. The AD9929 offers four preprogrammed MSHUT patterns that are selectable using the MSHUTPAT register. The preprogrammed length is the same for all patterns set by the MSHUTLEN register, but the active on period of the MSHUT pulse is different for each pattern, as shown in Figure 57. Figure 58 shows an example of selecting MSHUTPAT0 positioned to start 3 lines after the falling edge of VD, with MSHUTLEN = 5.
HD
MSHUTPAT0
MSHUTPAT1
MSHUTPAT2 MSHUTPAT3 MSHUTLEN + 1
04593-0-059
Figure 57. MSHUT Patterns Available by Setting MSHUTPAT Register
VD
HD 1 XVSG1XVSG2 2 3 1 2 3 4 5
tEXP
XSUBCK
MSHUTPOS = 3
MSHUTPAT = 0, MSHUTLEN = 5
Figure 58. Example of MSHUT Timing with MSHUTEN = 1 and MSHUTPOS_HP = 0
Rev. A | Page 50 of 64
04593-0-060
MSHUT
AD9929
MSHUT High Precision Operation
The MSHUTPOS_HP register allows fine precision control of the MSHUT position within a line. Under normal MSHUT operation when MSHUTPOS_HP = 0, the MSHUT polarity changes from high to low on the negative edge of the HD pulse, as shown in Figure 53. By using the MSHUTPOS_HP register, the rising and falling edges of MSHUT can be delayed by multiples of the OL counter length that has been set in the OLEN register. For example, if MSHUTPOS_HP = 3, the MSHUT rising and falling edges are delayed by three OL counter cycles after the falling edge of HD, as shown in Figure 56. Figure 56 provides an example of high precision MSHUT and SUBCK timing. In this example, the length of the OL counter is shorter. This provides finer precision control of the placement of the MSHUT pulse within a line.
VD
HD 1 XVSG1XVSG2 2 3 1 2 3 4 5
tEXP
XSUBCK
OL COUNTER
OL COUNTER
OL OL COUNTER COUNTER
MSHUTPOS = 3
MSHUTPAT = 0, MSHUTLEN = 5
Figure 59. Example of MSHUT High Precision Timing MSHUTEN = 1 and MSHUTPOS_HP = 3
VD
HD 1 XVSG1XVSG2 2 3 1 2 3 4 5
tEXP
XSUBCK
MSHUT
MSHUT DELAY = 3 OL COUNTER LENGTHS MSHUTPOS = 3 MSHUTPAT = 0, MSHUTLEN = 5
04593-0-062
NOTES 1MSHUT OUTPUT IN NORMAL OPERATION WITH MSHUTPOS_HP = 0 2MSHUT OUTPUT IN HIGH PRECISION OPERATION WITH MSHUTPOS_HP = 3
Figure 60. Example of MSHUT High Precision Timing MSHUTEN = 1, MSHUTPOS_HP = 3, with XSUBCKMODE_HP = 1, XSUBCKNUM_HP = 3
Rev. A | Page 51 of 64
04593-0-061
MSHUT
AD9929
STROBE TIMING
The AD9929 provides a STROBE output pulse that can be used to trigger the camera flash circuit. STROBE operation is set by only one register, as described in Table 32. The STROBE output is held low when STROBE_EN (Address 0x0B) is set to 0 and enabled when set to 1. Providing STROBE_EN = 1, the STROBE
SET STROBE_EN (ADDRESS 0x0B) = 1
output pulse is asserted high on the rising edge of the last XSUBCK pulse in the field, as shown in Figure 61. Also shown in Figure 61, the STROBE pulse is asserted low again on the rising edge of VSG.
VD
XVSG1XVSG2
tEXP
XSUBCK
STROBE 1 NOTES 1. STROBE OUTPUT ASSERTED HIGH ON RISING EDGE OF LAST XSUBCK PULSE 2. STROBE OUTPUT ASSERTED LOW ON NEGATIVE EDGE OF XVSG PULSE
2
04593-0-063
Figure 61. STROBE Output Timing
VD
HD 3ns MIN CLI
H-COUNTER RESET
H-COUNTER RESET
NOTES 1. INTERNAL 12-BIT H-GRAY CODE COUNTER IS RESET 7 CLOCK CYCLES AFTER THE HD FALLING EDGE.
Figure 62. External VD/HD and Internal 12-Bit H-Gray Code Counter Synchronization, Slave Mode
Rev. A | Page 52 of 64
04593-0-064
H-GRAY CODE COUNTER X (PIXEL COUNTER)
X
X
X
X
X
X
X
X
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
1
2
3
4
AD9929 DIGITAL I/O STATES FOR DIFFERENT OPERATING CONDITIONS
Table 38 describes the state of the digital I/Os for different operating conditions. Table 38. I/O Levels
I/O DCLK1 DCLK2 VD2 HD2 RG H1 H2 V1 V2 V3 V4 SUBCK STROBE MSHUT FD OCONT_REG1 = 0 ACTIVE ACTIVE H H L H L VL VL VL VL SUBVDD L L H DIGSTBY H ACTIVE H H L H L VL VL VL VL VL L L L
1 2
OUTCONT_REG is a register setting located at Address 0x05. It defaults to 0 at power-up. VD and HD operate in master mode.
Rev. A | Page 53 of 64
AD9929 POWER SUPPLY SEQUENCING
The recommended power-up and power-down sequences are shown in Figure 64 and Figure 65, respectively. As shown, the VM1 and VM2 voltage level should never exceed the VH1 and VH2 voltage level during power-up or power-down. Excessive current results if this requirement is not met due to a PN junction diode turning on between the VM1/2 and VH supply pins. Figure 63 describes the AD9929 AFETG and V-driver supplies associated with vertical driver outputs.
AVDD,TCVDD, HVDD,RGVDD, DVDD,DRVDD
RECOMMENDED POWER-UP SUPPLY SEQUENCING
When the AD9929 is powered up, the following power supply sequence is recommended. Refer to Figure 64. 1. 2. Turn ON: VDD, DVDD, DRVDD, HVDD, RGVDD, TCVDD, and AVDD. Turn ON: VH1 VH2, VM1,VM2, and VL.
VDD
VM1
VM2
VH1
VL VH2
Caution: There is a PN junction diode from VM1 and VM2 to VH. Excessive current occurs if the VM1 and VM2 supply level is greater than VH1 and VH2 supplies.
XV1 XV2 TIMING GENERATOR XV3 XV4 XVSG1 XVSG2 SUBCK (VH2, VL) XSUBCK
04593-0-065
V1 (VH1, VM1, VL) V2 (VM2, VL) V-DRIVER LOGIC V3 (VH1, VM1, VL) V4 (VM2, VL)
RECOMMENDED POWER-DOWN SUPPLY SEQUENCING
When the AD9929 is powered down, the following power supply sequence is recommended. Refer to Figure 65. 1. 2. Turn OFF: VH1, VH2, VM1, VM2, and VL. Turn OFF: VDD, DVDD, DRVDD, HVDD, RGVDD, TCVDD, and AVDD.
Figure 63. Block Diagram of AD9929 Showing Timing Generator and Vertical Driver
VH1 = VH2 = 15.0V
VDD = DVDD = DRVDD = HVDD = RGVDD = TCVDD = AVDD = 3V
1 0V
2 VM1 = VM2 = -0.5V
SAME TIME AS VM AND VH OR EARLIER, BUT NOT BEFORE VDD REACHES 3V.
Figure 64. Power-Up Supply Sequencing
VH1 = VH2 = 15.0V
VDD = DVDD = DRVDD = HVDD = RGVDD = TCVDD = AVDD = 3V
1 VM1 = VM2 = -0.5V
2 0V
VL = -7.5V
04593-0-067
SAME TIME AS VM AND VH OR EARLIER, BUT NOT AFTER VDD.
Figure 65. Power-Down Supply Sequencing
Rev. A | Page 54 of 64
04593-0-066
VL = -7.5V
AD9929
INITIAL START-UP SEQUENCE
Recommended Start-Up Sequence for Master Mode
When the AD9929 is powered up, the following sequence is recommended (refer to Figure 66 for each step). 1. 2. 3. Turn on power supplies as described in the Power Supply Sequencing section. Apply the CLI master clock input. CLI is output on DCLK2 Pin 16 at this time. Reset the internal AD9929 registers. Write a 0x000000 to the SW_RESET register (Address 0x00). This sets all internal register values to their default values. (This step is optional because there is an internal power-on reset circuit that is applied at power-up.) Program DIGSTBY and AFESTBY registers (Address 0x05) = 1 and all other necessary control registers.
AD9929 POWER-UP SEQUENCE
5. 6. 7. 8.
Program system registers (Address 0x20). Program Mode_A registers (Address 0x21). Program Mode_B registers (Address 0x22). Program OUTCONT_REG register (Address 0x05) = 1. (The internal OUTCONT signal is asserted high at this time. This enables the digital outputs.) Program control register MODE (Address 0x0A) = 0. This selects Mode_A operation. (This step is optional because the AD9929 defaults to Mode_A at power-up.)
9.
10. Program control register MODE (Address 0x0A) = 1. This selects Mode_B operation. Note: Complete this write at least 4 CLI cycles before the start of the next field.
4.
CLI (INPUT)
OUTCONT1 (INTERNAL SIGNAL)
tPWR
SERIAL WRITES
3
5
7
1V
ODD FIELD VD (OUTPUT) 1H
EVEN FIELD
ODD FIELD
HD (OUTPUT) H1, VSUB, FD DIGITAL (OUTPUTS) H2, RG, MSHUT, STROBE
tDELAY3
DCLK22 (OUTPUT)
DCLK1 (OUTPUT)
tSETTLING4
NOTES 1OUTCONT IS AN INTERNAL SIGNAL THAT IS CONTROLLED USING REGISTER OUTCONT_REG (ADDRESS 0x05). 2DCLK2 WILL BE OUTPUT ON THE FD/DCLK2 PIN 16 PROVIDING REGISTER DCLK2SEL (ADDRESS 0xD5) = 1. THE DCLK2SEL REGISTER DEFAULTS TO 1 AT POWER-UP. 3IT TAKES 11 CLI CLOCKS FROM WHEN OCONT GOES HIGH UNTIL VD, HD, AND DIGITAL OUTPUT DATA IS VALID. 4THERE IS A 500S SETTLING TIME FROM WHEN THE DIGSTBY REGISTER IS SET TO WHEN THE DCLK1 IS STABLE.
Figure 66. Recommended Start-Up Sequence and Synchronization, Master Mode
Rev. A | Page 55 of 64
04593-0-068
AD9929
STANDBY MODE OPERATION
Recommended Standby Mode Sequence
When the AD9929 is going into standby operation, the following sequence is recommended (refer to Figure 67 for each step). 1. Program OUTCONT_REG (Address 0x05) = 0. This asserts the internal OUTCONT signal low, causing all digital outputs to become disabled. Program registers AFESTBY (Address 0x05) = 0 and DIGSTBY (Address 0x05) = 0. The AD9929 is now in standby operation. 4. 5. 6. 3. When ready to come out of standby operation, program register DIGSTBY (Address 0x05) = 1 and register AFESTBY (Address 0x05) = 1. Program necessary control registers. Program control register MODE (Address 0x0A) = 0. This selects Mode_A operation. Program register OUTCONT_REG (Address 0x05) = 1. This asserts the internal OUTCONT signal high, causing all digital outputs to become active.
2.
AD9929 SUPPLIES
CLI (INPUT)
OUTCONT (INTERNAL SIGNAL)
1 SERIAL WRITES
2
3
5
6
VD (OUTPUT)
HD (OUTPUT)
H1, VSUB DIGITAL OUTPUTS H2, RG, MSHUT, STROBE, FD
tDELAY2
DCLK1 AND DCLK21
AFESTBY (REGISTER)
DIGSTBY (REGISTER)
NOTES 1DCLK2 WILL BE OUTPUT ON THE FD/DCLK2 PIN 16 PROVIDING REGISTER DCLK2SEL (ADDRESS 0xD5) = 1. 2IT TAKES 11 CLI CLOCKS FROM WHEN OCONT GOES HIGH UNTIL VD, HD, AND DIGITAL OUTPUT DATA IS VALID.
Figure 67. Recommended Standby Sequence
Rev. A | Page 56 of 64
04593-0-069
AD9929
SHUT-DOWN MODE OPERATION
Recommended Power-Down Sequence
When the AD9929 is going to be powered down, the following sequence is recommended (refer to Figure 68 for each step). 1. 2. 3.
VDD (INPUT)
Program OUTCONT_REG (Address 0x05) = 0. Program registers AFESTBY (Address 0x05) = 0 and DIGSTBY (Address 0x05) = 0. Remove power from AD9929.
4
CLI (INPUT)
OUTCONT (INTERNAL)
SERIAL WRITES
VD (OUTPUT)
ODD FIELD
EVEN FIELD
ODD FIELD
HD (OUTPUT)
H1, VSUB DIGITAL OUTPUTS H2, RG, MSHUT, STROBE
DCLK1
DCLK21
AFESTBY (REGISTER)
DIGSTBY (REGISTER)
04593-0-070
NOTE
1DCLK2
WILL BE OUTPUT ON THE FD/DCLK2 PIN 16 PROVIDING REGISTER DCLK2SEL (ADDRESS 0xD5) = 1.
Figure 68. Recommended Shut-Down Sequence
Rev. A | Page 57 of 64
AD9929
APPLICATIONS WHERE THE CLI CLOCK FREQUENCY CHANGES DURING OPERATION
The AD9929 must be reset, as described in Figure 69, if the CLI clock frequency is changed during operation. The DCLK1 output can become unstable if this reset sequence is not applied after any changes in the CLI clock frequency.
FAST
SLOW
FAST
CL
t1
1 SERIAL WRITES 2 3 4
OUTCONT (INTERNAL SIGNAL)
VD (OUTPUT)
HD (OUTPUT)
HD, VD, H1, (SUBCK = VH2)
OUTPUTS
(V1, V2, V3, V4 = VL), H2, STROBE, MSHUT REGION A REGION B
tDELAY*
DCLK1I
REGION C
DIG_STBY (REGISTER)
SERIAL PROGRAMMING STEPS MUST BE FOLLOWED WHEN THE CLI CLOCK FREQUENCY CHANGES 1. OUTCONT_REG = 0 2. DIG_STBY = 0 3. DIG_STBY = 1 4. OUTCONT_REG = 1 NOTES ABOUT REGIONS A, B, AND C 1DIGITAL OUTPUTS MAY BECOME INVALID IN REGION A 2DIGITAL OUTPUTS ARE OUTPUT AS SHOWN IN REGION B 3DCLK1 OUTPUT MAY BECOME INVALID IN REGION C 4APPLICATIONS SHOULD NOT USE OUTPUT SIGNALS IN REGION C
04593-0-071
t1 = MINIMUM OF 2 CLI CLOCK CYCLES
*IT TAKES 4 CLI CLOCK CYCLES FROM WHEN OUTCONT GOES HIGH UNTIL VD, HD AND DIGITAL OUTPUT DATA IS VALID.
Figure 69. Reset Sequence That Must Be Applied when Changing the CLI Clock Frequency During Operation
Rev. A | Page 58 of 64
AD9929
CCD SIGNAL t SHP SHD CYCLE 1 CLI (tOD + tVCLIDLY) OUTPUT DATA N - 10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N CYCLE 2 CYCLE 3 CYCLE 4 CYCLE 5 CYCLE 6 CYCLE 7 CYCLE 8 CYCLE 9 N
ID
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
tID tS1
NOTES 1. RECOMMENDED PLACEMENT FOR CLI RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES. 3. OUTPUT DATA LATENCY IS NINE CYCLES.
Figure 70. Output Data Pipeline Delay
Rev. A | Page 59 of 64
04593-0-075
AD9929 CIRCUIT LAYOUT INFORMATION
The AD9929 typical circuit connection is shown in Figure 71. The PCB layout is critical in achieving good image quality from the AD9929 product. All of the supply pins must be decoupled to ground with good quality, high frequency chip capacitors. The 0.1 F decoupling capacitors should be located as close as possible to the supply pins, and should have a very low inductance path to a continuous ground plane. There should also be a 4.7 F or larger capacitor for each main supply, although it is not necessary for each individual pin. In most applications it is easier and recommended to share the same supply for AVDD, DVDD, TCVDD, RGVDD, and HVDD, as long as the individual supply pins are separately bypassed at each supply pin. A separate 3 V supply should be used for DRVDD with this supply pin decoupled to the same ground plane as the rest of the chip. A separate ground for DRVSS is not recommended. The vertical driver VM supply pins can be connected to individual supplies or to the same supply, depending on the application requirement for the mid-level voltage on the vertical outputs. These pins may also be directly connected to the common ground plane, as shown in Figure 71. The analog bypass pins, REFB, REFT, should also be carefully decoupled to ground as close as possible to their respective pins. The analog input, CCDIN, capacitor should also be located close to the pin. The H1, H2, and RG printed circuit board traces should be designed to have low inductance to avoid excessive distortion of the signals. Heavier traces are recommended because of the large transient current demand by the CCD on H1 and H2. If possible, physically locate the AD9929 close to the CCD to reduce the inductance on these lines. As always, the routing path should be as direct as possible from the AD9929 to the CCD. Careful trace impedance considerations must also be made with applications using a flex printed circuit (FPC) connecting the CCD to the AD9929. FPC trace impedances can be controlled by applying a solid uniform ground plane under the H1, H2, and RG traces. This helps minimize the amount of overshoot and ringing on these signals at the CCD inputs.
Rev. A | Page 60 of 64
AD9929
3V DRIVER SUPPLY
4.7F
DATA OUTPUTS
12
DCLK1
VSUB TO CCD
0.1F
D6 DRVDD
DRVSS
DCLK1 A1
VSUB
D8 D9 D10 D11
A3 B3
D7
D4 D5
D3
D1 D2
D0
3V ANALOG SUPPLY
B2 A2
A4
B4
B5 A5
B6
A6
A7 B7
A8
B8
A9
TO MECHANICAL SHUTTER CIRCUIT TO STROBE CIRCUIT FD/DCLK2 VD TO ASIC/DSP HD TO ASIC/DSP 3V ANALOG SUPPLY 0.1F
MSHUT STROBE FD/DCLK2 VD HD HVDD HVSS HVSS HVSS H2 H1
B1 C2 C1 D1 D2 E1 E2 F2 G2 F1 G1 H1 H2 J1 J2 K1
PIN 1 IDENTIFIER
A10 B10 B9 C9 C10 D9 D10 E9 E10 F9 F10 G9 G10 H9 H10 J10
DVDD VDD DVSS SYNC/VGATE VM1 0.1F 0.1F
10k
SYNC/VGATE
OUTCONT V1
V2 VH2 VL VM2 SUBCK V3 V4 VH1 SCK
OUTCONT
AD9929
TOP VIEW (Not to Scale)
VL SUPPLY 0.1F 4.7F 5 V1-V4, SUBCK TO CCD
H1, H2 AND RG TO CCD 3V ANALOG SUPPLY
3
RG RGVSS RGVDD CLI TCVSS
MASTER CLOCK INPUT 0.1F
K9 K10
K2
K3
K4 J4
K5 J6 K6
J7 J8 K7
K8
J3
J5
J9
VH SUPPLY 0.1F 4.7F
AVSS AVSS AVSS
TCVDD
AVDD
AVSS CCDIN
AVSS REFT REFB
AVSS
AVSS AVSS
3V ANALOG SUPPLY 4.7F
0.1F 0.1F
0.1F
1.0F 1.0F
VDVSS SDATA
SL
3
SERIAL INTERFACE
04593-0-072
CCD SIGNAL
Figure 71. AD9929 Typical Circuit Configuration
Rev. A | Page 61 of 64
AD9929 OUTLINE DIMENSIONS
9.00 BSC SQ A1 CORNER INDEX AREA
10 9 8 7 6 5 43 21 A
BALL A1 INDICATOR TOP VIEW BOTTOM VIEW
B C D E F G H J K
0.90 REF SQ 7.20 BSC 1.00 0.85 1.40 MAX DETAIL A 0.25 MIN
DETAIL A
0.12 MAX COPLANARITY 0.55 SEATING 0.50 PLANE 0.45 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-205-AB
0.80 BSC
Figure 72. 64-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-64) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9929BBCZ1 Temperature Range -25C to +85C Package Description 64-Lead Plastic Ball Grid Array Package Option BC-64
1
Z = Pb-free part.
Rev. A | Page 62 of 64
AD9929 NOTES
Rev. A | Page 63 of 64
AD9929 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04593-0-1/04(A)
Rev. A | Page 64 of 64

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